IS42S16100E IC42S16100E 512K Words x 16 Bits x 2 Banks (16-MBIT) JANUARY 2008 SYNCHRONOUS DYNAMIC RAM FEATURES DESCRIPTION Clock frequency: 200, 166, 143 MHz ISSIs 16Mb Synchronous DRAM IS42S16100E/ IC42S16100E is organized as a 524,288-word x 16-bit Fully synchronous all signals referenced to a x 2-bank for improved performance. The synchronous positive clock edge DRAMs achieve high-speed data transfer using pipeline Two banks can be operated simultaneously and architecture. All inputs and outputs signals refer to the independently rising edge of the clock input. Dual internal bank controlled by A11 (bank select) PIN CONFIGURATIONS 50-Pin TSOP (Type II) Single 3.3V power supply LVTTL interface VDD 1 50 GND Programmable burst length DQ0 2 49 DQ15 DQ1 3 48 IDQ14 (1, 2, 4, 8, full page) GNDQ 4 47 GNDQ DQ2 5 46 DQ13 Programmable burst sequence: DQ3 6 45 DQ12 Sequential/Interleave VDDQ 7 44 VDDQ 43 DQ4 8 DQ11 2048 refresh cycles every 32 ms DQ5 9 42 DQ10 GNDQ 10 41 GNDQ Random column address every clock cycle DQ6 11 40 DQ9 DQ7 12 39 DQ8 Programmable CAS latency (2, 3 clocks) VDDQ 13 38 VDDQ LDQM 14 37 NC Burst read/write and burst read/single write WE 15 36 UDQM CAS 16 35 CLK operations capability RAS 17 34 CKE Burst termination by burst stop and CS 18 33 NC 32 A11 19 A9 precharge command A10 20 31 A8 A0 21 30 A7 Byte controlled by LDQM and UDQM A1 22 29 A6 A2 23 28 A5 Packages 400-mil 50-pin TSOP-II and 60-ball A3 24 27 A4 BGA VDD 25 26 GND Lead-free package option Available in Industrial Temperature PIN DESCRIPTIONS A0-A11 Address Input CAS Column Address Strobe Command A0-A10 Row Address Input WE Write Enable A11 Bank Select Address LDQM Lower Bye, Input/Output Mask A0-A7 Column Address Input UDQM Upper Bye, Input/Output Mask DQ0 to DQ15 Data DQ VDD Power CLK System Clock Input GND Ground CKE Clock Enable VDDQ Power Supply for DQ Pin CS Chip Select GNDQ Ground for DQ Pin RAS Row Address Strobe Command NC No Connection Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. C 01/22/08IS42S16100E, IC42S16100E PIN CONFIGURATION PACKAGE CODE: B 60 BALL FBGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch) 1 2 3 4 5 6 7 A VSS DQ15 DQ0 VDD B DQ14 VSSQ VDDQ DQ1 C DQ13 VDDQ VSSQ DQ2 D DQ4 DQ3 DQ12 DQ11 E DQ10 VSSQ VDDQ DQ5 F DQ9 VDDQ VSSQ DQ6 G DQ8 NC NC DQ7 H NC NC VDD NC J NC UDQM LDQM WE K NC CLK CAS RAS L CKE NC CS NC M A11 A9 NC NC N A8 A7 A10 A0 P A6 A5 A1 A2 R VSS A4 VDD A3 PIN DESCRIPTIONS A0-A10 Row Address Input WE Write Enable A0-A7 Column Address Input LDQM, UDQM x16 Input/Output Mask A11 Bank Select Address Vdd Power DQ0 to DQ15 Data I/O Vss Ground CLK System Clock Input Vddq Power Supply for I/O Pin CKE Clock Enable Vssq Ground for I/O Pin CS Chip Select NC No Connection RAS Row Address Strobe Command CAS Column Address Strobe Command 2 Integrated Silicon Solution, Inc. www.issi.com Rev. C 01/22/08