IS42S83200J, IS42S16160J IS45S83200J, IS45S16160J SEPTEMBER 2020 32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM OVERVIEW FEATURES ISSI s 256Mb Synchronous DRAM achieves high-speed Clock frequency: 166, 143, 133 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 256Mb SDRAM is organized as follows. Internal bank for hiding row access/precharge IS42/45S83200J IS42/45S16160J Single Power supply: 3.3V + 0.3V 8M x 8 x 4 Banks 4M x16x4 Banks LVTTL interface 54-pin TSOPII 54-pin TSOPII Programmable burst length 54-ball BGA 54-ball BGA (1, 2, 4, 8, full page) Programmable burst sequence: KEY TIMING PARAMETERS Sequential/Interleave Parameter -6 -7 Unit Auto Refresh (CBR) Clk Cycle Time Self Refresh CAS Latency = 3 6 7 ns CAS Latency = 2 10 7.5 ns 8K refresh cycles every 32 ms (A2 grade) or Clk Frequency 64 ms (commercial, industrial, A1 grade) CAS Latency = 3 166 143 Mhz Random column address every clock cycle CAS Latency = 2 100 133 Mhz Programmable CAS latency (2, 3 clocks) Access Time from Clock CAS Latency = 3 5.4 5.4 ns Burst read/write and burst read/single write CAS Latency = 2 5.4 5.4 ns operations capability Burst termination by burst stop and precharge command ADDRESS TABLE OPTIONS Parameter 32M x 8 16M x 16 Package: Configuration 8M x 8 x 4 4M x 16 x 4 banks banks 54-pin TSOP-II Refresh Count 54-ball BGA Com./Ind. 8K/64ms 8K/64ms Operating Temperature Range: A1 8K/64ms 8K/64ms o o Commercial (0 C to +70 C) A2 8K/32ms 8K/32ms o o Industrial (-40 C to +85 C) Row Addresses A0-A12 A0-A12 o o Automotive Grade A1 (-40 C to +85 C) Column Addresses A0-A9 A0-A8 o o Automotive Grade A2 (-40 C to +105 C) Bank Address Pins BA0, BA1 BA0, BA1 Auto Precharge Pins A10/AP A10/AP Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap- plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. C4 09/17/2020IS42S83200J, IS42S16160J IS45S83200J, IS45S16160J DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 256Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function random-access memory designed to operate in 3.3V Vdd enabled. Precharge one bank while accessing one of the and 3.3V Vddq memory systems containing 268,435,456 other three banks will hide the precharge cycles and provide bits. Internally configured as a quad-bank DRAM with a seamless, high-speed, random-access operation. synchronous interface. Each 67,108,864-bit bank is orga- nized as 8,192 rows by 512 columns by 16 bits or 8,192 SDRAM read and write accesses are burst oriented starting rows by 1,024 columns by 8 bits. at a selected location and continuing for a programmed number of locations in a programmed sequence. The The 256Mb SDRAM includes an AUTO REFRESH MODE, registration of an ACTIVE command begins accesses, and a power-saving, power-down mode. All signals are followed by a READ or WRITE command. The ACTIVE registered on the positive edge of the clock signal, CLK. command in conjunction with address bits registered are All inputs and outputs are LVTTL compatible. used to select the bank and row to be accessed (BA0, The 256Mb SDRAM has the ability to synchronously burst BA1 select the bank A0-A12 select the row). The READ data at a high data rate with automatic column-address or WRITE commands in conjunction with address bits generation, the ability to interleave between internal banks registered are used to select the starting column location to hide precharge time and the capability to randomly for the burst access. change column addresses on each clock cycle during Programmable READ or WRITE burst lengths consist of burst access. 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx 16x 4 BANKS SHOWN) CLK DQML CKE DQMH COMMAND DATA IN CS DECODER BUFFER RAS 16 16 & CAS CLOCK WE REFRESH MODE 2 DQ 0-15 GENERATOR CONTROLLER REGISTER 13 VDD/VDDQ SELF DATA OUT REFRESH A10 BUFFER Vss/VssQ CONTROLLER 16 16 A12 A11 A9 A8 REFRESH A7 COUNTER A6 A5 8192 A4 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW ROW A0 ADDRESS ADDRESS BA0 LATCH BUFFER BA1 13 13 SENSE AMP I/O GATE 512 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. www.issi.com Rev. C4 09/17/2020 MULTIPLEXER ROW DECODER