IS42/45S81600F IS42/45S16800F 16Mx8, 8Mx16 SEPTEMBER 2019 128Mb SYNCHRONOUS DRAM OVERVIEW FEATURES ISSI s 128Mb Synchronous DRAM achieves high-speed Clock frequency: 200, 166, 143 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 128Mb SDRAM is organized as follows. Internal bank for hiding row access/precharge Power supply Vdd Vddq IS42/45S81600F IS42/45S16800F IS42/45S81600F 3.3V 3.3V 4M x8 x4 Banks 2M x16 x4 Banks IS42/45S16800F 3.3V 3.3V 54-pin TSOPII 54-pin TSOPII LVTTL interface 54-ball BGA Programmable burst length (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave KEY TIMING PARAMETERS Auto Refresh (CBR) Parameter -5 -6 -7 Unit Self Refresh Clk Cycle Time 4096 refresh cycles every 16 ms (A2 grade) or CAS Latency = 3 5 6 7 ns CAS Latency = 2 10 10 7.5 ns 64 ms (Commercial, Industrial, A1 grade) Clk Frequency Random column address every clock cycle CAS Latency = 3 200 166 143 Mhz Programmable CAS latency (2, 3 clocks) CAS Latency = 2 100 100 133 Mhz Burst read/write and burst read/single write Access Time from Clock operations capability CAS Latency = 3 5 5.4 5.4 ns CAS Latency = 2 6.5 6.5 5.4 ns Burst termination by burst stop and precharge command Temperature Ranges: o o Commercial (0 C to +70 C) o o Industrial (-40 C to +85 C) o o Automotive, A1 (-40 C to +85 C) o o Automotive, A2 (-40 C to +105 C) Copyright 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with - out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. D1 09/11/2019IS42/45S81600F, IS42/45S16800F DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 128Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE func- random-access memory designed to operate in 3.3V Vdd tion enabled. Precharge one bank while accessing one of and 3.3V Vddq memory systems containing 134,217,728 the other three banks will hide the precharge cycles and bits. Internally configured as a quad-bank DRAM with provide seamless, high-speed, random-access operation. a synchronous interface. Each 33,554,432-bit bank is organized as 4,096 rows by 512 columns by 16 bits or SDRAM read and write accesses are burst oriented starting 4,096 rows by 1,024 columns by 8 bits. at a selected location and continuing for a programmed number of locations in a programmed sequence. The The 128Mb SDRAM includes an AUTO REFRESH MODE, registration of an ACTIVE command begins accesses, and a power-saving, power-down mode. All signals are followed by a READ or WRITE command. The ACTIVE registered on the positive edge of the clock signal, CLK. command in conjunction with address bits registered are All inputs and outputs are LVTTL compatible. used to select the bank and row to be accessed (BA0, The 128Mb SDRAM has the ability to synchronously burst BA1 select the bank A0-A11 select the row). The READ data at a high data rate with automatic column-address or WRITE commands in conjunction with address bits generation, the ability to interleave between internal banks registered are used to select the starting column location to hide precharge time and the capability to randomly for the burst access. change column addresses on each clock cycle during Programmable READ or WRITE burst lengths consist of burst access. 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 2MX16X4 BANKS ONLY) CLK DQML CKE DQMH COMMAND DATA IN CS DECODER BUFFER RAS 16 16 & CAS CLOCK WE REFRESH MODE 2 DQ 0-15 GENERATOR CONTROLLER REGISTER 12 VDD/VDDQ SELF DATA OUT REFRESH A10 BUFFER Vss/VssQ CONTROLLER 16 16 A11 A9 A8 A7 REFRESH A6 COUNTER A5 A4 4096 A3 4096 MEMORY CELL A2 4096 ARRAY A1 4096 12 A0 BANK 0 ROW ROW BA0 ADDRESS ADDRESS BA1 LATCH BUFFER 12 12 SENSE AMP I/O GATE 512 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. www.issi.com Rev. D1 09/11/2019 MULTIPLEXER ROW DECODER