IS42S32160B IS45S32160B 16M x 32 512Mb SYNCHRONOUS DRAM DECEMBER 2009 OVERVIEW FEATURES ISSI s 512Mb Synchronous DRAM achieves high-speed Clock frequency: 166, 143 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 512Mb SDRAM is organized in 4Meg x 32 bit x 4 Banks. Internal bank for hiding row access/precharge Single Power supply: 3.3V + 0.3V KEY TIMING PARAMETERS LVTTL interface Programmable burst length Parameter -6 -7 -75E Unit (1, 2, 4, 8, full page) Clk Cycle Time CAS Latency = 3 6 7 ns Programmable burst sequence: CAS Latency = 2 10 10 7.5 ns Sequential/Inter leave Clk Frequency Auto Refresh (CBR) CAS Latency = 3 166 143 Mhz CAS Latency = 2 100 100 133 Mhz Self Refresh Access Time from Clock 8192 refresh cycles ever y 16ms (A2 grade) or CAS Latency = 3 5.4 5.4 ns 64 ms (Commercial, Industr ial, A1 grade) CAS Latency = 2 6.5 6.5 5.5 ns Random column address ever y clock cycle Programmable CAS latency (2, 3 clocks) Burst read/wr ite and burst read/single wr ite ADDRESS TABLE operations capability Parameter 16M x 32 Burst ter mination by burst stop and precharge command Configuration 4M x 32 x 4 banks Refresh Count Com./Ind. 8K / 64ms OPTIONS A1 8K / 64ms Package: 86-pin TSOP-II A2 8K / 16ms 90-ball W-BGA Row Addresses A0 A12 Operating Temperature Range: Column A0 A8 o o Commercial (0 C to +70 C) Addresses o o Industr ial (-40 C to +85 C) Bank Address BA0, BA1 o o Automotive Grade, A1 (-40 C to +85 C) Pins o o Automotive Grade, A2 (-40 C to +105 C) Autoprecharge A10/AP Pins Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - www.issi.com 1 Rev. A 11/30/09IS42S32160B, IS45S32160B DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 512Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function random-access memor y designed to operate in 3.3V Vdd enabled. Precharge one bank while accessing one of the and 3.3V Vddq memor y systems containing 536,870,912 other three banks will hide the precharge cycles and provide bits. Inter nally configured as a quad-bank DRAM with seamless, high-speed, random-access operation. a synchronous interface. Each 134,217,728-bit bank is organized as 8,192 rows by 512 columns by 32 bits SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed The 512Mb SDRAM includes an AUTO REFRESH MODE, number of locations in a programmed sequence. The and a power-saving, power-down mode. All signals are registration of an ACTIVE command begins accesses, registered on the positive edge of the clock signal, CLK. followed by a READ or WRITE command. The ACTIVE All inputs and outputs are LVTTL compatible. command in conjunction with address bits registered are The 512Mb SDRAM has the ability to synchronously burst used to select the bank and row to be accessed (BA0, data at a high data rate with automatic column-address BA1 select the bank A0-A12 select the row). The READ generation, the ability to interleave between internal banks or WRITE commands in conjunction with address bits to hide precharge time and the capability to randomly registered are used to select the starting column location change column addresses on each clock cycle during for the burst access. burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst ter minate option. FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx 32x 4 BANKS) CLK DQM0- CKE DQM3 DATA IN COMMAND CS BUFFER DECODER RAS 32 32 & CAS CLOCK WE REFRESH MODE 4 GENERATOR DQ 0-31 CONTROLLER REGISTER 13 SELF V DD /VDDQ DATA OUT REFRESH A10 Vss/Vss Q BUFFER CONTROLLER 32 32 A12 A11 A9 A8 REFRESH A7 COUNTER A6 A5 8192 A4 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW A0 ROW ADDRESS ADDRESS BA0 LATCH BUFFER BA1 13 13 SENSE AMP I/O GATE 512 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. - www.issi.com Rev. A 11/30/09 MULTIPLEXER ROW DECODER