IS42S32200E 512K Bits x 32 Bits x 4 Banks (64-MBIT) ADVANCED INFORMATION JUNE 2008 SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW ISSI s 64Mb Synchronous DRAM IS42S32200E is organized Clock frequency: 200, 166, 143 MHz as 524,288 bits x 32-bit x 4-bank for improved performance. Fully synchronous all signals referenced to a The synchronous DRAMs achieve high-speed data transfer positive clock edge using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. Internal bank for hiding row access/precharge Single 3.3V power supply LVTTL interface Programmable burst length: KEY TIMING PARAMETERS (1, 2, 4, 8, full page) Parameter -5 -6 -7 Unit Programmable burst sequence: Sequential/Interleave Clk Cycle Time CAS Latency = 3 5 6 7 ns Self refresh modes CAS Latency = 2 10 10 10 ns 4096 refresh cycles every 64 ms Clk Frequency Random column address every clock cycle CAS Latency = 3 200 166 143 Mhz CAS Latency = 2 100 100 100 Mhz Programmable CAS latency (2, 3 clocks) Access Time from Clock Burst read/write and burst read/single write CAS Latency = 3 4.5 5.5 5.5 ns operations capability CAS Latency = 2 7.5 7.5 8 ns Burst termination by burst stop and precharge command Available in Industrial temperature grade Available in 400-mil 86-pin TSOP II and 90-ball BGA Available in Lead free Power Down and Deep Power Down Mode Partial Array Self Refresh Temperature Compensated Self Refresh Output Driver Strength Selection Please contact Production Manager for Mobile function detail. Copyright 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 1 Rev. 00D 06/02/08IS42S32200E GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic function enabled. Precharge one bank while accessing one random-access memory designed to operate in 3.3V of the other three banks will hide the precharge cycles and memory systems containing 67,108,864 bits. Internally provide seamless, high-speed, random-access operation. configured as a quad-bank DRAM with a synchronous SDRAM read and write accesses are burst oriented starting interface. Each 16,777,216-bit bank is organized as 2,048 at a selected location and continuing for a programmed rows by 256 columns by 32 bits. number of locations in a programmed sequence. The The 64Mb SDRAM includes an AUTO REFRESH MODE, registration of an ACTIVE command begins accesses, and a power-saving, power-down mode. All signals are followed by a READ or WRITE command. The ACTIVE registered on the positive edge of the clock signal, CLK. command in conjunction with address bits registered are All inputs and outputs are LVTTL compatible. used to select the bank and row to be accessed (BA0, BA1 select the bank A0-A10 select the row). The READ or The 64Mb SDRAM has the ability to synchronously burst WRITE commands in conjunction with address bits reg- data at a high data rate with automatic column-address istered are used to select the starting column location for generation, the ability to interleave between internal banks the burst access. to hide precharge time and the capability to randomly change column addresses on each clock cycle during Programmable READ or WRITE burst lengths consist of burst access. 1, 2, 4 and 8 locations or full page, with a burst terminate option. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE FUNCTIONAL BLOCK DIAGRAM CLK DQM0-3 CKE COMMAND DATA IN CS BUFFER DECODER RAS 32 32 CAS & CLOCK WE REFRESH MODE GENERATOR DQ 0-31 CONTROLLER REGISTER 11 SELF VDD/VDDQ DATA OUT REFRESH GND/GNDQ A10 BUFFER CONTROLLER 32 32 A9 A8 A7 REFRESH A6 COUNTER A5 A4 2048 A3 2048 MEMORY CELL A2 2048 ARRAY A1 2048 11 A0 BANK 0 ROW ROW BA0 ADDRESS ADDRESS BA1 LATCH BUFFER 11 11 SENSE AMP I/O GATE 256 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 2 Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774 Rev. 00D 06/02/08 MULTIPLEXER ROW DECODER