IS42S32800J IS45S32800J 8M x 32 256Mb SYNCHRONOUS DRAM DECEMBER 2021 OVERVIEW FEATURES ISSI s 256Mb Synchronous DRAM achieves high-speed Clock frequency:166, 143, 133 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 256Mb SDRAM is organized in 2Meg x 32 bit x 4 Banks. Internal bank for hiding row access/precharge Single Power supply: 3.3V + 0.3V KEY TIMING PARAMETERS LVTTL interface Parameter -6 -7 -75E Unit Programmable burst length (1, 2, 4, 8, full page) Clk Cycle Time Programmable burst sequence: CAS Latency = 3 6 7 ns Sequential/Interleave CAS Latency = 2 10 10 7.5 ns Auto Refresh (CBR) Clk Frequency CAS Latency = 3 166 143 Mhz Self Refresh CAS Latency = 2 100 100 133 Mhz 4096 refresh cycles every 16ms (A2 grade) or Access Time from Clock 64 ms (Commercial, Industrial, A1 grade) CAS Latency = 3 5.4 5.4 ns Random column address every clock cycle CAS Latency = 2 6.5 6.5 6 ns Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write ADDRESS TABLE operations capability Parameter 8M x 32 Burst termination by burst stop and precharge command Configuration 2M x 32 x 4 banks Refresh Count Com./Ind. 4K / 64ms OPTIONS A1 4K / 64ms Package: 90-ball TF-BGA, 86-pin TSOP2 A2 4K / 16ms Row Addresses A0 A11 Operating Temperature Range: o o Commercial (0 C to +70 C) Column A0 A8 o o Industrial (-40 C to +85 C) Addresses o o Automotive Grade, A1 (-40 C to +85 C) Bank Address BA0, BA1 o o Automotive Grade, A2 (-40 C to +105 C) Pins Autoprecharge A10/AP Pins Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - www.issi.com 1 Rev. B1 12/01/2021IS42S32800J, IS45S32800J DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 256Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function random-access memory designed to operate in 3.3V Vdd enabled. Precharge one bank while accessing one of the and 3.3V Vddq memory systems containing 268,435,456 other three banks will hide the precharge cycles and provide bits. Internally configured as a quad-bank DRAM with a seamless, high-speed, random-access operation. synchronous interface. Each 67,108,864-bit bank is orga- nized as 4,096 rows by 512 columns by 32 bits. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed The 256Mb SDRAM includes an AUTO REFRESH MODE, number of locations in a programmed sequence. The and a power-saving, power-down mode. All signals are registration of an ACTIVE command begins accesses, registered on the positive edge of the clock signal, CLK. followed by a READ or WRITE command. The ACTIVE All inputs and outputs are LVTTL compatible. command in conjunction with address bits registered are The 256Mb SDRAM has the ability to synchronously burst used to select the bank and row to be accessed (BA0, data at a high data rate with automatic column-address BA1 select the bank A0-A11 select the row). The READ generation, the ability to interleave between internal banks or WRITE commands in conjunction with address bits to hide precharge time and the capability to randomly registered are used to select the starting column location change column addresses on each clock cycle during for the burst access. burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 2Mx 32x 4 BANKS) CLK DQM0 - DQM3 CKE COMMAND DATA IN CS 4 DECODER BUFFER RAS 32 32 & CAS CLOCK WE REFRESH MODE DQ 0-31 GENERATOR CONTROLLER REGISTER 12 VDD/VDDQ SELF DATA OUT REFRESH A10 BUFFER Vss/VssQ CONTROLLER 32 32 A11 A9 A8 A7 REFRESH A6 COUNTER A5 A4 4096 A3 4096 MEMORY CELL A2 4096 ARRAY A1 4096 12 A0 BANK 0 ROW ROW BA0 ADDRESS ADDRESS BA1 LATCH BUFFER 12 12 SENSE AMP I/O GATE 512 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. - www.issi.com Rev. B1 12/01/2021 MULTIPLEXER ROW DECODER