IS42/45SM/RM/VM16200D 1M x 16Bits x 2Banks Low Power Synchronous DRAM Description These IS42SM/RM/VM16200D are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features JEDEC standard 3.3V, 2.5V, 1.8V power supply All inputs and outputs referenced to the positive edge of the Auto refresh and self refresh system clock All pins are compatible with LVCMOS interface Data mask function by DQM 4K refresh cycle / 64ms Internal dual banks operation Programmable Burst Length and Burst Type Burst Read Single Write operation - 1, 2, 4, 8 or Full Page for Sequential Burst Special Function Support - 4 or 8 for Interleave Burst - PASR(Partial Array Self Refresh) Programmable CAS Latency : 2,3 clocks - Auto TCSR(Temperature Compensated Self Refresh) - Programmable Driver Strength Control - Full Strength or 1/2, 1/4, of Full Strength - Deep Power Down Mode Automatic precharge, includes CONCURRENT Auto Precharge Mode and controlled Precharge Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 www.issi.com - dram issi.com Rev. A November 2015 IS42/45SM/RM/VM16200D Figure1: 54Ball FBGA Ball Assignment 1 2 3 4 5 6 7 8 9 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE /CAS /RAS /WE G NC NC A9 BA NC /CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Top View 2 www.issi.com - dram issi.com Rev. A November 2015