IS42VM83200D / IS42VM16160D / IS42VM32800D 32Mx8, 16Mx16, 8Mx32 APRIL 2012 256Mb Mobile Synchronous DRAM FEATURES DESCRIPTION Fully synchronous all signals referenced to a ISSI s 256Mb Mobile Synchronous DRAM achieves high- positive clock edge speed data transfer using pipeline architecture. All input and output signals refer to the rising edge of the clock Internal bank for hiding row access and pre- input. Both write and read accesses to the SDRAM are charge burst oriented. The 256Mb Mobile Synchronous DRAM Programmable CAS latency: 2, 3 is designed to minimize current consumption making it Programmable Burst Length: 1, 2, 4, 8, and Full ideal for low-power applications. Both TSOP and BGA Page packages are offered, including industrial grade products. Programmable Burst Sequence: Sequential and Interleave KEY TIMING PARAMETERS Auto Refresh (CBR) TCSR (Temperature Compensated Self Refresh) (1) (2) Parameter -8 -12 Unit PASR (Partial Arrays Self Refresh): 1/16, 1/8, CLK Cycle Time 1/4, 1/2, and Full CAS Latency = 3 8 12 ns Deep Power Down Mode (DPD) CAS Latency = 2 10 - ns Driver Strength Control (DS): 1/4, 1/2, and Full CLK Frequency CAS Latency = 3 125 83 Mhz OPTIONS Configurations: CAS Latency = 2 100 - Mhz 32M x 8 Access Time from CLK 16M x 16 CAS Latency = 3 6 10 ns 8M x 32 CAS Latency = 2 9 - ns Power Supply IS42VMxxx Vdd /Vddq = 1.8V Notes: 1. Available for x8/x16 only Packages: 2. Available for x32 only x8 TSOP II (54) x16 TSOP II (54), BGA (54) x32 TSOP II (86), BGA (90) Temperature Range: Commercial (0C to +70C) Industrial (40 C to 85 C) ADDRESSING TABLE Parameter 32M x 8 16M x 16 8M x 32 Configuration 8M x 8 x 4 banks 4M x 16 x 4 banks 2M x 32 x 4 banks Refresh Count 8K/64ms 8K/64ms 4K/64ms Row Addressing A0-A12 A0-A12 A0-A11 Column Addressing A0-A9 A0-A8 A0-A8 Bank Addressing BA0, BA1 BA0, BA1 BA0, BA1 Precharge Addressing A10 A10 A10 Copyright 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - www.issi.com 1 Rev. A 04/11/2012IS42VM83200D / IS42VM16160D / IS42VM32800D General Description ISSIs 256Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 1.8V Vdd / Vddq memory systems containing 268,435,456 bits. Internally configured as a quad-bank DRAM with a synchronous interface. The 256Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVCMOS (VDD = 1.8V) compatible. The 256Mb SDRAM has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed number of locations in a programmed sequence. The registration of an Active command begins accesses, followed by a Read or Write command. The ACTIVE command in conjunction with address bits registered are used to select the bank and row to be accessed (BA0, BA1 select the bank A0-A12 (x8 and x16) and A0-A11 (x32) select the row). The READ or WRITE commands in conjunction with address bits registered are used to select the starting column location for the burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations, or full page, with a burst terminate option. FUNCTIONAL BLOCK DIAGRAM (FOR 16Mx 16 BANKS SHOWN) CLK DQML CKE DQMH DATA IN COMMAND CS BUFFER DECODER RAS 16 16 & CAS CLOCK WE REFRESH MODE 2 GENERATOR DQ 0-15 CONTROLLER REGISTER 13 SELF VDD/VDDQ DATA OUT REFRESH A10 Vss/VssQ BUFFER CONTROLLER 16 16 A12 A11 A9 A8 REFRESH A7 COUNTER A6 A5 8192 A4 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW A0 ROW ADDRESS ADDRESS BA0 LATCH BUFFER BA1 13 13 SENSE AMP I/O GATE 512 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. - www.issi.com Rev. A 04/11/2012 MULTIPLEXER ROW DECODER