IS43/46DR16128 SEPTEMBER 2012 2Gb (x16) DDR2 SDRAM FEATURES Clock frequency up to 333MHz (667 MT/s Data Rate) Bidirectional differential Data Strobe (Single-ended 8 internal banks for concurrent operation data-strobe is an optional feature) 4-bit prefetch architecture On-Chip DLL aligns DQ and DQs transitions with CK transitions Programmable CAS Latency: 3, 4, 5, 6 and 7 DQS can be disabled for single-ended data strobe Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Differential clock inputs CK and CK Write Latency = Read Latency-1 VDD and VDDQ = 1.8V 0.1V Programmable Burst Sequence: Sequential or PASR (Partial Array Self Refresh) Interleave SSTL 18 interface Programmable Burst Length: 4 and 8 tRAS lockout supported Automatic and Controlled Precharge Command Operating temperature: Power Down Mode Commercial (T = 0C to 70C T = 0C to 85C) A C Auto Refresh and Self Refresh 2 Industrial (T = -40C to 85C T = -40C to 95C) A C Refresh Interval: 7.8 s (8192 cycles/64 ms) 2 Automotive, A1 (T = -40C to 85C T = -40C to 95C) A C OCD (Off-Chip Driver Impedance Adjustment) 2 Automotive, A2 (T = -40C to 105C T = -40C to 105C) A C ODT (On-Die Termination) Weak Strength Data-Output Driver Option OPTIONS ADDRESS TABLE Parameter 128Mx16 Configuration: Row Addressing A0-A13 128Mx16 (two stacked 16M x 8 x8 banks) Column Addressing A0-A9 Package: Bank Addressing BA0-BA2 84-ball FBGA Precharge Addressing A10 Clock Cycle Timing -37C -3D Units Speed Grade DDR2-533C DDR2-667D CL-tRCD-tRP 4-4-4 5-5-5 tCK tCK (CL=3) 5 5 ns tCK (CL=4) 3.75 3.75 ns tCK (CL=5) 3.75 3 ns tCK (CL=6) 3.75 3 ns tCK (CL=7) 3.75 3 ns Frequency (max) 266 333 MHz Note: 1. The -37C device specifications is shown for reference only. 2. Please contact ISSI for availability of Automotive parts. Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B, 09/6/2012 IS43/46DR16128 DDR2 SDRAM (128Mx16) BGA Ball-out (Top-View) (10.5mm x 13.5mm Body, 0.8mm pitch) Symbol Description Note: VDDL and VSSDL are power and ground for the DLL. CK, CK Input clocks CKE Clock enable CS Chip Select RAS ,CAS ,WE Command control inputs A 13:0 Address BA 2:0 Bank Address DQ 15:0 I/O UDQS, UDQS Upper Byte Data Strobe LDQS, LDQS Lower Byte Data Strobe UDM, LDM Input data mask VDD Supply voltage VSS Ground VDDQ DQ power supply VSSQ DQ ground VREF Reference voltage VDDL DLL power supply VSSDL DLL ground ODT On Die Termination Enable NC No connect Integrated Silicon Solution, Inc. www.issi.com 2 Rev. B, 09/6/2012