IS43/46DR16160B 16Mx16 DDR2 DRAM DECEMBER 2017 FEATURES DESCRIPTION Vdd = 1.8V 0.1V, Vddq = 1.8V 0.1V ISSI s 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The JEDEC standard 1.8V I/O (SSTL 18-compatible) double-data rate architecture is essentially a 4n-prefetch Double data rate interface: two data transfers per architecture, with an interface designed to transfer two clock cycle data words per clock cycle at the I/O balls. Differential data strobe (DQS, DQS) 4-bit prefetch architecture On chip DLL to align DQ and DQS transitions with ADDRESS TABLE CK Parameter 16M x 16 4 internal banks for concurrent operation Configuration 4M x 16 x 4 Programmable CAS latency (CL) 3, 4, 5, 6 and 7 sup- banks ported Refresh Count 8K/64ms Posted CAS and programmable additive latency (AL) Row Addressing 8K (A0-A12) 0, 1, 2, 3, 4, 5 and 6 supported Column 512 (A0-A8) WRITE latency = READ latency - 1 tCK Addressing Programmable burst lengths: 4 or 8 Bank Addressing BA0, BA1 Adjustable data-output drive strength, full and re- Precharge A10 duced strength options Addressing On-die termination (ODT) OPTIONS Configuration: KEY TIMING PARAMETERS 16Mx16 (4Mx16x4 banks) IS43/46DR16160B Speed Grade -25D -3D -37C Package: 84-ball TW-BGA (8mm x 12.5mm) tRCD 12.5 15 15 Timing Cycle time tRP 12.5 15 15 2.5ns CL=5 DDR2-800D tRC 55 55 55 2.5ns CL=6 DDR2-800E tRAS 40 40 40 3.0ns CL=5 DDR2-667D 3.75ns CL=4 DDR2-533C tCK CL=3 5 5 5 5.0ns CL=3 DDR2-400B tCK CL=4 3.75 3.75 3.75 Temperature Range: tCK CL=5 2.5 3 Commercial (0C Tc 85C) Industrial (-40C Tc 95C -40C Ta 85C) tCK CL=6 2.5 Automotive, A1 (-40C Tc 95C -40C Ta 85C) Automotive, A2 (-40C Tc Ta 105C) Tc = Case Temp, Ta = Ambient Temp Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B 12/11/2017IS43/46DR16160B GENERAL DESCRIPTION Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location (A0-A8) for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. FUNCTIONAL BLOCK DIAGRAM DMa - DMb Notes: 1. An:n = no. of address pins - 1 2. DQm: m = no. of data pins - 1 3. DMa - DMb = UDM, LDM DQSa - DQSb = UDQS, LDQS DQSa - DQSb = UDQS, LDQS 2 Integrated Silicon Solution, Inc. www.issi.com Rev. B 12/11/2017