IS43/46DR86400C IS43/46DR16320C 64Mx8, 32Mx16 DDR2 DRAM MARCH 2013 FEATURES DESCRIPTION ISSI s 512Mb DDR2 SDRAM uses a double-data-rate Vdd = 1.8V 0.1V, Vddq = 1.8V 0.1V architecture to achieve high-speed operation. The JEDEC standard 1.8V I/O (SSTL 18-compatible) double-data rate architecture is essentially a 4n-prefetch Double data rate interface: two data transfers architecture, with an interface designed to transfer two per clock cycle data words per clock cycle at the I/O balls. Differential data strobe (DQS, DQS) 4-bit prefetch architecture On chip DLL to align DQ and DQS transitions ADDRESS TABLE with CK Parameter 64M x 8 32M x 16 4 internal banks for concurrent operation Configuration 16M x 8 x 4 8M x 16 x 4 Programmable CAS latency (CL) 3, 4, 5, and 6 banks banks supported Refresh Count 8K/64ms 8K/64ms Posted CAS and programmable additive latency Row Addressing 16K (A0-A13) 8K (A0-A12) (AL) 0, 1, 2, 3, 4, and 5 supported Column 1K (A0-A9) 1K (A0-A9) WRITE latency = READ latency - 1 tCK Addressing Programmable burst lengths: 4 or 8 Bank Addressing BA0, BA1 BA0, BA1 Adjustable data-output drive strength, full and Precharge A10 A10 reduced strength options Addressing On-die termination (ODT) KEY TIMING PARAMETERS OPTIONS Configuration(s): Speed Grade -25D -3D 64Mx8 (16Mx8x4 banks) IS43/46DR86400C tRCD 12.5 15 32Mx16 (8Mx16x4 banks) IS43/46DR16320C tRP 12.5 15 Package: tRC 55 55 x8: 60-ball BGA (8mm x 10.5mm) tRAS 40 40 x16: 84-ball WBGA (8mm x 12.5mm) Timing Cycle time tCK CL=3 5 5 2.5ns CL=5 DDR2-800D tCK CL=4 3.75 3.75 2.5ns CL=6 DDR2-800E tCK CL=5 2.5 3 3.0ns CL=5 DDR2-667D tCK CL=6 2.5 3.75ns CL=4 DDR2-533C 5ns CL=3 DDR2-400B Temperature Range: Commercial (0C Tc 85C) Industrial (-40C Tc 95C -40C Ta 85C) Automotive, A1 (-40C Tc 95C -40C Ta 85C) Automotive, A2 (-40C Tc Ta 105C) Tc = Case Temp, Ta = Ambient Temp Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A 3/19/2013IS43/46DR86400C, IS43/46DR16320C GENERAL DESCRIPTION Read and write accesses to the DDR2 SDRAM are burst oriented accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select the bank A0-A12(x16) or A0-A13(x8) select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location A0-A9 for the burst access and to determine if the auto precharge A10 command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. FUNCTIONAL BLOCK DIAGRAM DMa - DMb RDQS, RDQS Notes: 1. An:n = no. of address pins - 1 2. DQm: m = no. of data pins - 1 3. For x8 devices: DMa - DMb = DM DQSa - DQSb = DQS DQSa - DQSb = DQS RDQS, RDQS available only for x8 4. For x16 devices: DMa - DMb = UDM, LDM DQSa - DQSb = UDQS, LDQS DQSa - DQSb = UDQS, LDQS 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A 3/19/2013