IS43LD16256A IS43LD32128A 4Gb (x16, x32) Mobile LPDDR2 S4 SDRAM FEBRUARY 2020 FEATURES DESCRIPTION The IS43LD16256A/32128A is 4Gbit CMOS LPDDR2 Low-voltage Core and I/O Power Supplies DRAM. The device is organized as 8 banks of 32Meg VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, words of 16bits or 16Meg words of 32bits. This product VDD1 = 1.70-1.95V uses a double-data-rate architecture to achieve high- High Speed Un-terminated Logic(HSUL 12) I/O speed operation. The double data rate architecture is Interface essentially a 4N prefetch architecture with an interface Clock Frequency Range : 10MHz to 533MHz designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous (data rate range : 20Mbps to 1066Mbps per I/O) operations referenced to both rising and falling edges of Four-bit Pre-fetch DDR Architecture the clock. The data paths are internally pipelined and 4n Multiplexed, double data rate, command/ad- bits prefetched to achieve very high bandwidth. dress inputs Eight internal banks for concurrent operation Bidirectional/differential data strobe per byte of data (DQS/DQS ) Programmable Read/Write latencies(RL/WL) ADDRESS TABLE and burst lengths(4,8 or 16) Parameter 128Mx32 256Mx16 ZQ Calibration Row Addresses R0-R13 R0-R13 On-chip temperature sensor to control self re- Column Addresses C0-C9 C0-C10 fresh rate Bank Addresses BA0-BA2 BA0-BA2 Partial array self refresh(PASR) Refresh Count 8192 8192 Deep power-down mode(DPD) Operation Temperature Commercial (TC = 0C to 85C) (1) KEY TIMING PARAMETERS Industrial (TC = -40C to 85C) Speed Data Write Read tRCD/ OPTIONS Grade Rate Latency Latency tRP Configuration: (Mb/s) 256Mx16 (32M x 16 x 8 banks) -18 1066 4 8 Typical 128Mx32 (16M x 32 x 8 banks) -25 800 3 6 Typical Package: 168-ball PoP BGA -3 667 2 5 Typical Notes: 1. Other clock frequencies/data rates supported please refer to AC timing tables. 2. Please contact ISSI for Fast trcd /trp . Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A1 02/10/2020IS43LD16256A IS43LD32128A 168-ball FBGA - 12mm x 12mm, 0.5mm pitch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A A DNU DNU NC NC NC NC NC NC NC NC V V DQ30 DQ29 V DQ26 DQ25 V DQS 3 V V DNU DNU DD1 SSQ SSQ SSQ DD1 SS 1 1 B B DNU DNU V NC V NC NC V NC V V DQ31 V DQ28 DQ27 V DQ24 DQS3 V DM3 V DNU DNU DD1 SS SS SS DD2 DDQ DDQ DDQ DD2 C C V V DQ15 V SS DD2 SSQ D NC NC V DQ14 D DDQ E E NC NC DQ12 DQ13 1 F F NC V DQ11 V SS SSQ G NC NC V DQ10 G DDQ H H NC NC DQ8 DQ9 1 J NC V DQS1 V J SS SSQ K NC NC V DQS 1 K DDQ L L NC NC V DM1 DD2 M NC V V V M SS REFDQ SS N NC V V DM0 N DD1 DD1 P ZQ V DQS 0 V P REFCA SSQ R V V V DQS0 R SS DD2 DDQ T CA9 CA8 DQ6 DQ7 T U CA7 V DQ5 V U DDCA SSQ V V CA6 V DQ4 V SSCA DDQ CA5 V DQ2 DQ3 W W DDCA Y CK CK DQ1 V Y SSQ AA V V V DQ0 AA SS DD2 DDQ AB DNU DNU CS NC V CA1 V CA3 CA4 V V DQ16 V DQ18 DQ20 V DQ22 DQS2 V DM2 V DNU DNU AB DD1 SSCA DD2 SS DDQ DDQ DDQ DD2 1 AC DNU DNU CKE NC V CA0 CA2 V V NC NC V DQ17 DQ19 V DQ21 DQ23 V DQS 2 V V DNU DNU AC SS DDCA SS SSQ SSQ SSQ DD1 SS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Top View (ball down) Note: 1 1. Balls labeled Vss (at coordinates B5, B8, F2, J2, AC9) may be connected to Vss or left unconnected. 2. Balls indicated as (NC) are no connects. 3. For x16, DQ16-DQ31, DQS2-DQS3, DQS2 -DQS3 , DM3-DM4 are no connects. 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A1 02/10/2020