IS43/46LR16200D 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43LR16200D is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features JEDEC standard 1.8V power supply 64ms refresh period (4K cycle) Two internal banks for concurrent operation Auto & self refresh MRS cycle with address key programs Concurrent Auto Precharge - CAS latency 2, 3 (clock) Maximum clock frequency up to 166MHz - Burst length (2, 4, 8, 16) Maximum data rate up to 333Mbps/pin - Burst type (sequential & interleave) Power Saving support Fully differential clock inputs (CK, /CK) - PASR (Partial Array Self Refresh) All inputs except data & DM are sampled at the rising - Auto TCSR (Temperature Compensated Self Refresh) edge of the system clock - Deep Power Down Mode Data I/O transaction on both edges of data strobe - Programmable Driver Strength Control by Full Strength Bidirectional data strobe per byte of data (DQS) or 3/4, 1/2, 1/4, 1/8 of Full Strength DM for write masking only LVCMOS compatible inputs/outputs Edge aligned data & data strobe output Center aligned data & data strobe input Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its p roducts at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services de scribed herein. Customers are advised to obtain the latest version of this device specification before relying on any published information a nd before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 www.issi.com - dram issi.com Rev. B 03/27/2017IS43/46LR16200D Figure1: 60Ball FBGA Ball Assignment 1 2 3 4 5 6 7 8 9 A VSS DQ15 VSSQ VDDQ DQ0 VDD B VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ C VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ D VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ E VSSQ UDQS DQ8 DQ7 LDQS VDDQ F VSS UDM NC NC LDM VDD G CKE CK /CK /WE /CAS /RAS H A9 NC NC /CS BA NC J A6 A7 A8 A10 A0 A1 K VSS A4 A5 A2 A3 VDD Top View 2 www.issi.com - dram issi.com Rev. B 03/27/2017