IS43LR32800G, IS46LR32800G 2M x 32Bits x 4Banks Mobile DDR SDRAM Description The IS43/46LR32800G is 268,435,456 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 2,097,152 words x 32 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features JEDEC standard 1.8V power supply. 64ms refresh period (4K cycle) VDD = 1.8V, VDDQ = 1.8V Auto & self refresh Four internal banks for concurrent operation Concurrent Auto Precharge MRS cycle with address key programs Maximum clock frequency up to 200MHZ - CAS latency 2, 3 (clock) Maximum data rate up to 400Mbps/pin - Burst length (2, 4, 8, 16) Power Saving support - Burst type (sequential & interleave) - PASR (Partial Array Self Refresh) Fully differential clock inputs (CK, /CK) - Auto TCSR (Temperature Compensated Self Refresh) All inputs except data & DM are sampled at the rising - Deep Power Down Mode edge of the system clock - Programmable Driver Strength Control by Full Strength Data I/O transaction on both edges of data strobe or 3/4, 1/2, 1/4, 1/8 of Full Strength Bidirectional data strobe per byte of data (DQS) Status Register Read (SRR) DM for write masking only LVCMOS compatible inputs/outputs Edge aligned data & data strobe output Packages: Center aligned data & data strobe input - 90-Ball BGA -152-Ball PoP BGA Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances 1 Rev. A November 2013 www.issi.com - dram issi.com IS43LR32800G, IS46LR32800G Figure 1: 90Ball FBGA Ball Assignment 1 2 3 4 5 6 7 8 9 A VSS DQ31 VDDQ DQ16 VDD VSSQ B VDDQ DQ29 DQ17 DQ18 VSSQ DQ30 C VSSQ DQ27 DQ19 DQ20 VDDQ DQ28 D DQ21 VDDQ DQ25 DQ22 VSSQ DQ26 E VSSQ DQS3 DQ23 DQS2 VDDQ DQ24 F VDD DM3 NC DM2 VSS NC G CKE CLK /WE /CAS /RAS /CLK H /CS A9 A11 BA0 BA1 NC J A10 A6 A7 A0 A1 A8 K A2 A4 DM1 DM0 A3 A5 L DQ7 VSSQ DQS1 DQS0 VDDQ DQ8 M DQ5 VDDQ DQ9 DQ6 VSSQ DQ10 N DQ3 VSSQ DQ11 DQ4 VDDQ DQ12 P DQ1 VDDQ DQ13 DQ2 VSSQ DQ14 R VDDQ VSS DQ15 DQ0 VDD VSSQ Top View 2 Rev. A November 2013 www.issi.com - dram issi.com