IS43R83200D IS43/46R16160D, IS43/46R32800D 8Mx32,16Mx16, 32Mx8 JUNE2012 256MbDDRSDRAM FEATURES DEVICEO VERVIEW VDD andVDDQ: 2.5V 0.2V ISSIs 256-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word SSTL 2 compatible I/O accesses per clock cycle The. 268,435,456-bit memory Double-data rate architecture two data transfers array is internally organized as four banks of 64Mb to per clock cycle allow concurrent operations The. pipeline allows Read Bidirectional, data strobe (DQS) is transmitted/ and Write burst accesses to be virtually continuous, with received with data, to be used in capturing data the option to concatenate or truncate the b Theursts . at the receiver programmable features of burst length, burst sequence DQS is edge-aligned with data for READs and and CAS latency enable further advantages The. device centre-aligned with data fWRITEsor is available in 8-bit, 16-bit and 32-bit data word size Differential clock inputs (CK and CK) Input data is registered on the I/O pins on both edges DLL aligns DQ and DQS transitions with CK of Data Strobe signal(s), while output data is referenced transitions to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. Commands entered on each positive CK edge data and data mask referenced to both edges of DQS An Auto Refresh mode is provided, along with a Self Four internal banks for concurrent operation Refresh mode . All I/Os are SSTL 2 compatible. Data Mask for write data. DM masks write data ADDRESS TABLE at both rising and falling edges of data strobe Parameter 8Mx32 16Mx16 32Mx 8 Burst Length: 2, 4 and 8 BurstT ype: Sequential and Interleave mode Configuration 2M x 32 x 4 4M x 16 x 4 8M x 8 x 4 banks banks banks Programmable CAS latency: 2, 2.5 and 3 Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Auto Refresh and Self Refresh Modes Pins Auto Precharge Autoprecharge A8/AP A10/AP A10/AP TRAS Lockout supported RAP(t = RCDt ) Pins Row Address 4K(A0 A11) 8K(A0 A12) 8K(A0 A12) OPTIONS Column 512(A0 A7, 512(A0 A8) 1K(A0 A9) Configuration(s): 8Mx32, 16Mx16, 32Mx8 Address A9) Package(s): Refresh Count 144 Ball BGA (x32) Com./Ind./A1 4K / 64ms 8K / 64ms 8K / 64ms 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16) A2 4K / 16ms 8K / 16ms Lead-free package available Temperature Range: KEY TIMINGPARAMETERS Commercial (0C to +70C) SpeedGrade -5 -6 Units Industrial (-40C to +85C) Automotive, A1 (-40C to +85C) FCk Max CL = 3 200 167 MHz Automotive, A2 (-40C to +105C) FCk Max CL = 2.5 200 167 MHz FCk Max CL = 2 133 133 MHz Copyright 2012 Integrated Silicon Solution, Inc.All rights reserv ed.ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descrCustomersibed herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effProductsectiveness are. not authorized for use in such applications unless Integrated Silicon Solution, Inc.receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B 06/19/2012IS43R83200D IS43/46R16160D, IS43/46R32800D FUNCTIONAL BLOCK DIAGRAM (x 32) CK COMMAND CK DM0-DM3 DECODER DATA IN 4 CKE & BUFFER CS CLOCK 32 RAS 32 GENERATOR I/O 0-31 CAS REFRESH DQS0-DQS3 WE CONTROLLER Mode Registers and 4 Ext. Mode Registers SELF VDD/VDDQ DATA OUT REFRESH Vss/VssQ BUFFER CONTROLLER 14 32 32 A11 A10 A9 A8 REFRESH A7 COUNTER 2 A6 A5 4096 A4 12 4096 MEMORY CELL A3 4096 ARRAY A2 4096 12 A1 BANK 0 ROW A0 ROW ADDRESS BA0 ADDRESS LATCH 12 BUFFER BA1 12 12 SENSE AMP I/O GATE 2 512 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. Rev. B 06/19/2012 MULTIPLEXER ROW DECODER