IS43/46R83200F IS43/46R16160F IS43/46R32800F 8Mx32, 16Mx16, 32Mx8 OCTOBER 2016 DEVICE OVERVIEW 256Mb DDR SDRAM ISSIs 256-Mbit DDR SDRAM achieves high speed data FEATURES transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memor y VDD and VDDQ: 2.5V 0.2V array is inter nally organized as four banks of 64Mb to SSTL 2 compatible I/O allow concurrent operations. The pipeline allows Read Double-data rate architecture two data transfers and Write burst accesses to be virtually continuous, with per clock cycle the option to concatenate or tr uncate the bursts. The Bidirectional, data strobe (DQS) is transmitted/ programmable features of burst length, burst sequence received with data, to be used in capturing data and CAS latency enable fur ther advantages. The device at the receiver is available in 8-bit, 16-bit and 32-bit data word size DQS is edge-aligned with data for READs and Input data is registered on the I/O pins on both edges centre-aligned with data for WRITEs of Data Strobe signal(s), while output data is referenced Differential clock inputs (CK and CK) to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. DLL aligns DQ and DQS transitions with CK transitions An Auto Refresh mode is provided, along with a Self Commands entered on each positive CK edge data Refresh mode. All I/Os are SSTL 2 compatible. and data mask referenced to both edges of DQS ADDRESS TABLE Four inter nal banks for concurrent operation Parameter 8M x 32 16M x 16 32M x 8 Data Mask for wr ite data. DM masks wr ite data at both rising and falling edges of data strobe Configuration 2M x 32 x 4 4M x 16 x 4 8M x 8 x 4 Burst Length: 2, 4 and 8 banks banks banks Burst Type: Sequential and Inter leave mode Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Pins Programmable CAS latency: 2, 2.5 and 3 Auto Refresh and Self Refresh Modes Autoprecharge A8/AP A10/AP A10/AP Pins Auto Precharge Row Address 4K(A0 A11) 8K(A0 A12) 8K(A0 A12) TRAS Lockout suppor ted (tRAP = tRCD) Column 512(A0 A7, 512(A0 A8) 1K(A0 A9) Address A9) OPTIONS Refresh Count Configuration(s): 8Mx32, 16Mx16, 32Mx8 Com./Ind./A1 4K / 64ms 8K / 64ms 8K / 64ms Package(s): A2 4K / 16ms 8K / 16ms 144 Ball BGA (x32) 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16) KEY TIMING PARAMETERS Lead-free package available Speed Grade -5 -6 Units Temperature Range: Commercial (0C to +70C) FCk Max CL = 3 200 167 MHz Industr ial (-40C to +85C) FCk Max CL = 2.5 167 167 MHz Automotive, A1 (-40C to +85C) FCk Max CL = 2 133 133 MHz Automotive, A2 (-40C to +105C) Copyright 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. B 10/18/2016IS43/46R83200F IS43/46R16160F, IS43/46R32800F FUNCTIONAL BLOCK DIAGRAM (x 32) CK COMMAND CK DM0-DM3 DECODER DATA IN 4 CKE & BUFFER CS CLOCK 32 RAS 32 GENERATOR I/O 0-31 CAS REFRESH DQS0-DQS3 WE CONTROLLER Mode Registers and 4 Ext. Mode Registers SELF VDD/VDDQ DATA OUT REFRESH Vss/VssQ BUFFER CONTROLLER 14 32 32 A11 A10 A9 A8 REFRESH A7 COUNTER 2 A6 A5 4096 A4 12 4096 MEMORY CELL A3 4096 ARRAY A2 4096 12 A1 BANK 0 ROW A0 ROW ADDRESS BA0 ADDRESS LATCH 12 BUFFER BA1 12 12 SENSE AMP I/O GATE 2 512 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. Rev. B 10/18/2016 MULTIPLEXER ROW DECODER