IS43/46R86400D IS43/46R16320D, IS43/46R32160D 16Mx32, 32Mx16, 64Mx8 MAY 2015 512Mb DDR SDRAM FEATURES DEVICE OVERVIEW VDD and VDDQ: 2.5V 0.2V (-6) ISSIs 512-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word VDD and VDDQ: 2.6V 0.1V (-5) accesses per clock cycle. The 536,870,912-bit memor y SSTL 2 compatible I/O array is inter nally organized as four banks of 128Mb to Double-data rate architecture two data transfers allow concurrent operations. The pipeline allows Read per clock cycle and Write burst accesses to be virtually continuous, with Bidirectional, data strobe (DQS) is transmitted/ the option to concatenate or tr uncate the bursts. The received with data, to be used in capturing data programmable features of burst length, burst sequence at the receiver and CAS latency enable fur ther advantages. The device DQS is edge-aligned with data for READs and is available in 8-bit, 16-bit and 32-bit data word size centre-aligned with data for WRITEs Input data is registered on the I/O pins on both edges Differential clock inputs (CK and CK) of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. DLL aligns DQ and DQS transitions with CK Commands are registered on the positive edges of CLK. transitions Commands entered on each positive CK edge An Auto Refresh mode is provided, along with a Self data and data mask referenced to both edges of Refresh mode. All I/Os are SSTL 2 compatible. DQS ADDRESS TABLE Four inter nal banks for concurrent operation Parameter 16M x 32 32M x 16 64M x 8 Data Mask for wr ite data. DM masks wr ite data at both rising and falling edges of data strobe Configuration 4M x 32 x 4 8M x 16 x 4 16M x 8 x 4 banks banks banks Burst Length: 2, 4 and 8 Burst Type: Sequential and Inter leave mode Bank Address BA0, BA1 BA0, BA1 BA0, BA1 Pins Programmable CAS latency: 2, 2.5 and 3 Autoprecharge A8/AP A10/AP A10/AP Auto Refresh and Self Refresh Modes Pins Auto Precharge Row Address 8K(A0 A12) 8K(A0 A12) 8K(A0 A12) T Lockout Suppor ted (t = t ) RAS RAP RCD Column 512(A0 A7, 1K(A0 A9) 2K(A0 A9, Address A9) A11) OPTIONS Refresh Count Configuration(s): 16Mx32, 32Mx16, and 64Mx8 Com./Ind./A1 8K / 64ms 8K / 64ms 8K / 64ms Package(s): 144 Ball BGA (x32), 66-pin TSOP-II A2 8K / 16ms 8K / 16ms 8K / 16ms (x8, x16), and 60 Ball BGA (x8, x16) Lead-free package KEY TIMING PARAMETERS Temperature Range: Speed Grade -5 -6 Units Commercial (0C to +70C) Fck Max CL = 3 200 167 MHz Industr ial (-40C to +85C) Fck Max CL = 2.5 167 167 MHz Automotive, A1 (-40C to +85C) Fck Max CL = 2 133 133 MHz Automotive, A2 (-40C to +105C) Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. D 05/18/2015IS43/46R86400D IS43/46R16320D, IS43/46R32160D FUNCTIONAL BLOCK DIAGRAM (x 32) CK COMMAND CK DM0-DM3 DECODER DATA IN 4 CKE & BUFFER CS CLOCK 32 RAS 32 GENERATOR I/O 0-31 CAS REFRESH DQS0-DQS3 WE CONTROLLER Mode Registers and 4 Ext. Mode Registers SELF VDD/VDDQ DATA OUT REFRESH Vss/VssQ A12 BUFFER CONTROLLER 15 32 32 A11 A10 A9 A8 REFRESH A7 COUNTER 2 A6 A5 8192 A4 13 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW A0 ROW ADDRESS BA0 ADDRESS LATCH 13 BUFFER BA1 13 13 SENSE AMP I/O GATE 2 512 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 9 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 9 2 Integrated Silicon Solution, Inc. Rev. D 05/18/2015 MULTIPLEXER ROW DECODER