Long-term Support IS43/46R86400F World Class Quality IS43/46R16320F 32Mx16, 64Mx8 DECEMBER 2016 512Mb DDR SDRAM FEATURES DEVICE OVERVIEW VDD and VDDQ: 2.5V 0.2V (-5, -6) ISSIs 512-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word VDD and VDDQ: 2.5V 0.1V (-4) accesses per clock cycle. The 536,870,912-bit memor y SSTL 2 compatible I/O array is inter nally organized as four banks of 128Mb to Double-data rate architecture two data transfers allow concurrent operations. The pipeline allows Read per clock cycle and Write burst accesses to be virtually continuous, with Bidirectional, data strobe (DQS) is transmitted/ the option to concatenate or tr uncate the bursts. The received with data, to be used in capturing data programmable features of burst length, burst sequence at the receiver and CAS latency enable fur ther advantages. The device DQS is edge-aligned with data for READs and is available in 8-bit and 16-bit word size. Input data is centre-aligned with data for WRITEs registered on the I/O pins on both edges of Data Strobe Differential clock inputs (CK and CK) signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are DLL aligns DQ and DQS transitions with CK registered on the positive edges of CLK. transitions Commands entered on each positive CK edge An Auto Refresh mode is provided, along with a Self data and data mask referenced to both edges of Refresh mode. All I/Os are SSTL 2 compatible. DQS Four inter nal banks for concurrent operation ADDRESS TABLE Data Mask for wr ite data. DM masks wr ite data Parameter 32M x 16 64M x 8 at both rising and falling edges of data strobe Configuration 8M x 16 x 4 16M x 8 x 4 Burst Length: 2, 4 and 8 banks banks Burst Type: Sequential and Inter leave mode Bank Address BA0, BA1 BA0, BA1 Programmable CAS latency: 2, 2.5 and 3 Pins Auto Refresh and Self Refresh Modes Autoprecharge A10/AP A10/AP Auto Precharge Pins Row Address 8K(A0 A12) 8K(A0 A12) OPTIONS Column 1K(A0 A9) 2K(A0 A9, Configuration(s): 32Mx16, 64Mx8 Address A11) Package(s): Refresh Count 66-pin TSOP-II Com./Ind./A1 8K / 64ms 8K / 64ms 60-ball BGA A2 8K / 16ms 8K / 16ms Lead-free package available Temperature Range: KEY TIMING PARAMETERS Commercial (0C to +70C) Speed Grade -4 -5 -6 Units Industr ial (-40C to +85C) Fck Max CL = 3 250 200 167 MHz Automotive, A1 (-40C to +85C) Fck Max CL = 2.5 167 167 167 MHz Automotive, A2 (-40C to +105C) Fck Max CL = 2 133 133 133 MHz Copyright 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. A 12/02/2016 Long-term Support IS43/46R86400F World Class Quality IS43/46R16320F FUNCTIONAL BLOCK DIAGRAM (x 16) CK COMMAND CK LDM, UDM DECODER DATA IN 2 CKE & BUFFER CS CLOCK 16 RAS GENERATOR 16 I/O 0-15 CAS REFRESH LDQS, UDQS WE Mode Registers and CONTROLLER 2 Ext. Mode Registers VDD/VDDQ SELF DATA OUT REFRESH Vss/VssQ A12 BUFFER 15 CONTROLLER 16 16 A11 A10 A9 A8 REFRESH A7 COUNTER 2 A6 A5 8192 A4 13 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 A0 ROW ROW ADDRESS BA0 ADDRESS LATCH 13 BA1 BUFFER 13 13 SENSE AMP I/O GATE 2 1024 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 10 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 10 2 Integrated Silicon Solution, Inc. Rev. A 12/02/2016 MULTIPLEXER ROW DECODER