IS43R32400D 4Mx32 SEPTEMBER2011 128MbDDRSDRAM FEATURES DEVICEO VERVIEW ISSIs 128-Mbit DDR SDRAM achieves high speed data Double-data rate architecture two data transfers transfer using pipeline architecture and two data word per clock cycle accesses per clock cycle The. 134,217,728-bit memory Bidirectional, data strobe (DQS) is transmitted/ array is internally organized as four banks of 32Mb to received with data, to be used in capturing data allow concurrent operations The. pipeline allows Read at the receiver and Write burst accesses to be virtually continuous, with DQS is edge-aligned with data for READs and the option to concatenate or truncate the b Theursts . centre-aligned with data fWRITEsor programmable features of burst length, burst sequence and CAS latency enable further advantages The. Differential clock inputs (CK and CK) device is available in 32-bit data word size Input data is DLL aligns DQ and DQS transitions with CK registered on the I/O pins on both edges of Data Strobe transitions signal(s), while output data is referenced to both edges Commands entered on each positive CK edge of Data Strobe and both edges of CLK.Commands are data and data mask referenced to both edges ofregistered on the positive edges of CLK. DQS An Auto Refresh mode is provided, along with a Self Four internal banks for concurrent operation Refresh mode . All I/Os are SSTL 2 compatible. Data Mask for write data. DM masks write data at both rising and falling edges of data strobe ADDRESS TABLE Burst Length: 2, 4 and 8 Parameter 4Mx32 BurstT ype: Sequential and Interleave mode Configuration 1M x 32 x 4 banks Programmable CAS latency: 2, 2.5, 3 and 4 Bank Address BA0, BA1 Auto Refresh and Self Refresh Modes Pins Auto Precharge Autoprecharge A8/AP Pins VDD andVDDQ: 2.5V 0.2V (-5, -6) Row Addresses 4K(A0 A11) VDD andVDDQ: 2.5V 0.125V (-4) Column Address 256(A0 A7) SSTL 2 compatible I/O Refresh Count 4K / 32ms OPTIONS Configuration(s): 4M x32 Package(s): KEY TIMINGP ARAMETERS 144 Ball BGA (x32) SpeedGrade -4 -5 -6 Units Lead-free package available Fck Max CL = 4 250 200 166 MHz Temperature Range: Fck Max CL = 3 200 200 166 MHz Commercial (0C to +70C) Fck Max CL = 2.5 166 166 MHz Industrial (-40C to +85C) Fck Max CL = 2 133 133 MHz Copyright 2011 Integrated Silicon Solution, Inc.All rights reserv ed.ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descrCustomersibed herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effProductsectiveness are. not authorized for use in such applications unless Integrated Silicon Solution, Inc.receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. A 09/07/2011 IS43R32400D FUNCTIONAL BLOCK DIAGRAM (x 32) CLK COMMAND CLK DM0-DM3 DECODER DATA IN 4 CKE & BUFFER CS CLOCK 32 RAS 32 GENERATOR I/O 0-31 CAS REFRESH DQS0-DQS3 WE CONTROLLER MODE 4 REGISTERS SELF VDD/VDDQ DATA OUT REFRESH Vss/VssQ A11 BUFFER CONTROLLER 14 32 32 A10 A9 A8 A7 REFRESH A6 COUNTER 2 A5 A4 4096 A3 12 4096 MEMORY CELL A2 4096 ARRAY A1 4096 12 A0 BANK 0 ROW ROW BA0 ADDRESS ADDRESS BA1 LATCH 12 BUFFER 14 12 SENSE AMP I/O GATE 256 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 8 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 8 2 Integrated Silicon Solution, Inc. Rev. A 09/07/2011 MULTIPLEXER ROW DECODER