IS42/45S16100F, IS42VS16100F 512K Words x 16 Bits x 2 Banks JUNE 2012 16Mb SDRAM FEATURES DESCRIPTION Clock frequency: ISSI s 16Mb Synchronous DRAM IS42S16100F, IS45S16100F and IS42VS16100F are each organized IS42/45S16100F: 200, 166, 143 MHz as a 524,288-word x 16-bit x 2-bank for improved IS42VS16100F: 133, 100 MHz performance. The synchronous DRAMs achieve high- Fully synchronous all signals referenced to a speed data transfer using pipeline architecture. All positive clock edge inputs and outputs signals refer to the rising edge of the clock input. Two banks can be operated simultaneously and independently ADDRESS TABLE Dual internal bank controlled by A11 Parameter IS42/45S16100F IS42VS16100F (bank select) Power Supply Vdd /Vddq 3.3V 1.8V Single power supply: Refresh Count 2K/32ms 2K/32ms IS42/45S16100F: Vdd /Vddq = 3.3V Row Addressing A0-A10 IS42VS16100F: Vdd /Vddq = 1.8V Column Addressing A0-A7 LVTTL interface Bank Addressing A11 Programmable burst length Precharge Addressing A10 (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave KEY TIMING PARAMETERS 2048 refresh cycles every 32 ms (1) (2) (2) (3) (3) Parameter -5 -6 -7 -75 -10 Unit Random column address every clock cycle CLK Cycle Time Programmable CAS latency (2, 3 clocks) CAS Latency = 3 5 6 7 7.5 10 ns Burst read/write and burst read/single write CAS Latency = 2 10 10 10 10 12 ns operations capability CLK Frequency Burst termination by burst stop and CAS Latency = 3 200 166 143 133 100 Mhz precharge command CAS Latency = 2 100 100 100 100 83 Mhz Byte controlled by LDQM and UDQM Access Time from Packages 400-mil 50-pin TSOP-II and 60-ball Clock BGA CAS Latency = 3 5 5.5 5.5 6 7 ns Lead-free package option CAS Latency = 2 6 6 6 8 8 ns Available in Industrial Temperature Notes: 1. Available for IS42S16100F only 2. Available for IS42S16100F and IS45S16100F only 3. Available for IS42VS16100F only Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A 06/13/2012IS42/45S16100F, IS42VS16100F PIN CONFIGURATIONS 50-Pin TSOP (Type II) VDD 1 50 VSS 49 DQ0 2 DQ15 DQ1 3 48 DQ14 VSSQ 4 47 VSSQ DQ2 5 46 DQ13 DQ3 6 45 DQ12 VDDQ 7 44 VDDQ DQ4 8 43 DQ11 DQ5 9 42 DQ10 VSSQ 10 41 VSSQ DQ6 11 40 DQ9 DQ7 12 39 DQ8 VDDQ 13 38 VDDQ LDQM 14 37 NC WE 15 36 UDQM CAS 16 35 CLK RAS 17 34 CKE CS 18 33 NC A11 19 32 A9 A10 20 31 A8 A0 21 30 A7 A1 22 29 A6 A2 23 28 A5 A3 24 27 A4 VDD 25 26 VSS PIN DESCRIPTIONS A0-A11 Address Input CAS Column Address Strobe Command A0-A10 Row Address Input WE Write Enable A11 Bank Select Address LDQM Lower Bye, Input/Output Mask A0-A7 Column Address Input UDQM Upper Bye, Input/Output Mask DQ0 to DQ15 Data DQ VDD Power CLK System Clock Input VSS Ground CKE Clock Enable VDDQ Power Supply for DQ Pin CS Chip Select VSSQ Ground for DQ Pin RAS Row Address Strobe Command NC No Connection 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A 06/13/2012