IS42S86400B IS42S16320B, IS45S16320B 64M x 8, 32M x 16 DECEMBER 2011 512Mb SYNCHRONOUS DRAM OVERVIEW FEATURES ISSI s 512Mb Synchronous DRAM achieves high-speed Clock frequency: 166, 143, 133 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 512Mb SDRAM is organized as follows . Interna lbank for hiding row access/precharge Power supply Vdd Vddq IS42S86400B IS42/45S16320B IS42/45S16320B 3.3V 3.3V 16Mx8x4 Banks 8M x16x4 Banks IS42S86400B 3.3V 3.3V 54-pin TSOPII 54-pin TSOPII LVTTL interface 54-ball W-BGA Programmable burst length (1, 2, 4, 8, full page) KEY TIMING PARAMETERS Programmable burst sequence: Parameter -6 -7 -75E Unit Sequential/Interleave Clk Cycle Time CAS Latency = 3 6 7 ns Auto Refresh (CBR) CAS Latency = 2 10 10 7.5 ns Self Refresh Clk Frequency 8K refresh cycles every 16ms (A2 grade) or CAS Latency = 3 166 143 Mhz 64 ms (Commercial, Industrial, A1 grade) CAS Latency = 2 100 100 133 Mhz Random column address every clock cycle Access Time from Clock CAS Latency = 3 5.4 5.4 ns Programmable CAS latency (2, 3 clocks) CAS Latency = 2 6 6 5.5 ns Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Available in 54-pinTSOP-II and 54-ballW -BGA (x16 only) Operating Temperature Range: o o Commercial: 0C to +70C o o Industrial: -40C to +85C o o Automotive, A1: -40C to +85C o o Automotive, A2: -40C to +105C Copyright 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice . ISSI assumes no liability arising out of the application or use of any information, products or services described Customers herein. are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiv Productseness. are not authorized for use in such ap- plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. H 12/01/2011IS42S86400B, IS42/45S16320B DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 512Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function random-access memory designed to operate in 3.3V Vdd enabled. Precharge one bank while accessing one of the and 3.3V Vddq memory systems containing 536,870,912 other three banks will hide the precharge cycles and provide bits. Internally configured as a quad-bank DRAM with a seamless, high-speed, random-access operation. synchronous interface. Each 134,217,728-bit bank is or- ganized as 8,192 rows by 1024 columns by 16 bits. Each SDRAM read and write accesses are burst oriented starting of the x8 s 134,217,728-bit banks is organized as 8,192 at a selected location and continuing for a programmed rows by 2048 columns by 8 bits. number of locations in a programmed sequence. The registration of an ACTIVE command begins accesses, The 512Mb SDRAM includes an AUTO REFRESH MODE, followed by a READ or WRITE command. The ACTIVE and a power-saving, power-down mode. All signals are command in conjunction with address bits registered are registered on the positive edge of the clock signal, CLK. used to select the bank and row to be accessed (BA0, All inputs and outputs are LVTTL compatible. BA1 select the bank A0-A12 select the row). The READ The 512Mb SDRAM has the ability to synchronously burst or WRITE commands in conjunction with address bits data at a high data rate with automatic column-address registered are used to select the starting column location generation, the ability to interleave between internal banks for the burst access. to hide precharge time and the capability to randomly Programmable READ or WRITE burst lengths consist of change column addresses on each clock cycle during 1, 2, 4 and 8 locations or full page, with a burst terminate burst access. option. FUNCTIONAL BLOCK DIAGRAM (FOR 8MX16X4 BANKS SHOWN) CLK DQML CKE DQMH COMMAND DATA IN CS DECODER BUFFER RAS 16 16 & CAS CLOCK WE REFRESH MODE 2 GENERATOR DQ 0-15 CONTROLLER REGISTER 13 SELF VDD/VDDQ DATA OUT REFRESH A10 Vss/VssQ BUFFER CONTROLLER 16 16 A12 A11 A9 A8 REFRESH A7 COUNTER A6 A5 8192 A4 8192 MEMORY CELL A3 8192 ARRAY A2 8192 13 A1 BANK 0 ROW A0 ROW ADDRESS ADDRESS BA0 LATCH BUFFER BA1 13 13 SENSE AMP I/O GATE 1024 (x 16) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 10 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 10 2 Integrated Silicon Solution, Inc. www.issi.com Rev. H 12/01/2011 MULTIPLEXER ROW DECODER