IS42S16400J
IS45S16400J
1 Meg Bits x 16 Bits x 4 Banks (64-MBIT)
AUGUST 2013
SYNCHRONOUS DYNAMIC RAM
FEATURES OVERVIEW
ISSI's 64Mb Synchronous DRAM is organized as 1,048,576
Clock frequency: 200, 166, 143, 133 MHz
bits x 16-bit x 4-bank for improved perfor mance. The
Fully synchronous; all signals referenced to a
synchronous DRAMs achieve high-speed data transfer
positive clock edge
using pipeline architecture. All inputs and outputs signals
Internal bank for hiding row access/precharge
refer to the rising edge of the clock input.
Single 3.3V power supply
LVTTL interface
Programmable burst length
KEY TIMING PARAMETERS
(1, 2, 4, 8, full page)
Programmable burst sequence:
Parameter -5 -6 -7 Unit
Sequential/Interleave
Clk Cycle Time
CAS Latency = 3 5 6 7 ns
Self refresh modes
CAS Latency = 2 7.5 7.5 7.5 ns
Auto refresh (CBR)
Clk Frequency
4096 refresh cycles ever y 64 ms (Com, Ind, A1
CAS Latency = 3 200 166 143 Mhz
grade) or 16ms (A2 grade)
CAS Latency = 2 133 133 133 Mhz
Random column address ever y clock cycle
Access Time from Clock
Programmable CAS latency (2, 3 clocks) CAS Latency = 3 4.8 5.4 5.4 ns
CAS Latency = 2 5.4 5.4 5.4 ns
Burst read/wr ite and burst read/single wr ite
operations capability
Burst ter mination by burst stop and precharge
command
ADDRESS TABLE
OPTIONS
Parameter 4M x 16
Package:
Configuration 1M x 16 x 4
54-pin TSOP II
banks
54-ball TF-BGA (8mm x 8mm)
Refresh Count
60-ball TF-BGA (10.1mm x 6.4mm)
Com./Ind. 4K/64ms
A1 4K/64ms
Operating Temperature Range
A2 4K/16ms
o o
Commercial (0 C to +70 C)
o o
Row Addresses A0-A11
Industrial (-40 C to +85 C)
o o
Column Addresses A0-A7
Automotive Grade A1 (-40 C to +85 C)
o o
Automotive Grade A2 (-40 C to +105 C) Bank Address Pins BA0, BA1
Auto Precharge Pins A10/AP
Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. www.issi.com 1
Rev. E
7/29/2013IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
other three banks will hide the precharge cycles and provide
random-access memor y designed to operate in 3.3V
seamless, high-speed, random-access operation.
memory systems containing 67,108,864 bits. Internally
SDRAM read and write accesses are burst oriented starting
configured as a quad-bank DRAM with a synchronous
at a selected location and continuing for a programmed
interface. Each 16,777,216-bit bank is organized as 4,096
number of locations in a programmed sequence. The
rows by 256 columns by 16 bits.
registration of an ACTIVE command begins accesses,
The 64Mb SDRAM includes an AUTO REFRESH MODE,
followed by a READ or WRITE command. The ACTIVE
and a power-saving, power-down mode. All signals are
command in conjunction with address bits registered are
registered on the positive edge of the clock signal, CLK.
used to select the bank and row to be accessed (BA0,
All inputs and outputs are LVTTL compatible.
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
The 64Mb SDRAM has the ability to synchronously burst
registered are used to select the starting column location
data at a high data rate with automatic column-address
for the burst access.
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
Programmable READ or WRITE burst lengths consist of
change column addresses on each clock cycle during
1, 2, 4 and 8 locations, or full page, with a burst terminate
burst access.
option.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
FUNCTIONAL BLOCK DIAGRAM
CLK
DQM
CKE
COMMAND DATA IN
CS
DECODER BUFFER
RAS
16 16
&
CAS
CLOCK
WE
REFRESH
MODE
DQ 0-15
A10 GENERATOR
CONTROLLER
REGISTER
12
VDD/VDDQ
SELF
DATA OUT
REFRESH
A11 BUFFER GND/GNDQ
CONTROLLER
16 16
A9
A8
A7
REFRESH
A6
COUNTER
A5
A4
4096
A3
4096
MEMORY CELL
A2
4096
ARRAY
A1 4096
12
A0
BANK 0
ROW
ROW
BA0
ADDRESS
ADDRESS
BA1
LATCH
BUFFER
12
12
SENSE AMP I/O GATE
256K
(x 16)
COLUMN
BANK CONTROL LOGIC
ADDRESS LATCH
8
BURST COUNTER
COLUMN DECODER
COLUMN
ADDRESS BUFFER
8
2 Integrated Silicon Solution, Inc. www.issi.com
Rev. E
7/29/2013
MULTIPLEXER
ROW DECODER