IS42S32200L IS45S32200L 512K Bits x 32 Bits x 4 Banks (64-MBIT) OCTOBER 2019 SYNCHRONOUS DYNAMIC RAM FEATURES OVERVIEW ISSI s 64Mb Synchronous DRAM IS42/45S32200L is Clock frequency: 200, 166, 143, 133 MHz organized as 524,288 bits x 32-bit x 4-bank for improved Fully synchronous all signals referenced to a performance. The synchronous DRAMs achieve high-speed positive clock edge data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. Internal bank for hiding row access/precharge Single 3.3V power supply LVTTL interface Programmable burst length: KEY TIMING PARAMETERS (1, 2, 4, 8, full page) Parameter -5 -6 -7 Unit Programmable burst sequence: Clk Cycle Time Sequential/Interleave CAS Latency = 3 5 6 7 ns Self refresh modes CAS Latency = 2 7.5 7.5 7.5 ns 4096 refresh cycles every 16ms (A2 grade) or Clk Frequency CAS Latency = 3 200 166 143 Mhz 64ms (Commercia, Industrial, A1 grade) CAS Latency = 2 133 133 133 Mhz Random column address every clock cycle Access Time from Clock Programmable CAS latency (2, 3 clocks) CAS Latency = 3 4.8 5.4 5.4 ns Burst read/write and burst read/single write CAS Latency = 2 5.4 5.4 5.4 ns operations capability Burst termination by burst stop and precharge command OPTIONS Packages: 86-pin TSOP-II 90-ball TF-BGA Operating temperature range: o o Commercial (0 C to + 70 C) o o Industrial (-40 C to + 85 C) o o Automotive Grade, A1 (-40 C to + 85 C) o o Automotive Grade, A2: (-40 C to +105 C) Copyright 2019 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex- pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A2 10/16/2019IS42S32200L, IS45S32200L GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic other three banks will hide the precharge cycles and provide random-access memory designed to operate in 3.3V seamless, high-speed, random-access operation. memory systems containing 67,108,864 bits. Internally SDRAM read and write accesses are burst oriented starting configured as a quad-bank DRAM with a synchronous at a selected location and continuing for a programmed interface. Each 16,777,216-bit bank is organized as 2,048 number of locations in a programmed sequence. The rows by 256 columns by 32 bits. registration of an ACTIVE command begins accesses, The 64Mb SDRAM includes an AUTO REFRESH MODE, followed by a READ or WRITE command. The ACTIVE and a power-saving, power-down mode. All signals are command in conjunction with address bits registered are registered on the positive edge of the clock signal, CLK. used to select the bank and row to be accessed (BA0, All inputs and outputs are LVTTL compatible. BA1 select the bank A0-A10 select the row). The READ or WRITE commands in conjunction with address bits The 64Mb SDRAM has the ability to synchronously burst registered are used to select the starting column location data at a high data rate with automatic column-address for the burst access. generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly Programmable READ or WRITE burst lengths consist of change column addresses on each clock cycle during 1, 2, 4 and 8 locations or full page, with a burst terminate burst access. option. A self-timed row precharge initiated at the end of the burst sequence is available with the AUTO PRECHARGE function enabled. Precharge one bank while accessing one of the FUNCTIONAL BLOCK DIAGRAM CLK DQM0-3 CKE DATA IN COMMAND CS BUFFER RAS DECODER 32 32 CAS & CLOCK WE REFRESH MODE DQ 0-31 GENERATOR CONTROLLER REGISTER 11 SELF VDD/VDDQ DATA OUT REFRESH A10 BUFFER GND/GNDQ CONTROLLER 32 32 A9 A8 A7 REFRESH A6 COUNTER A5 A4 2048 A3 2048 MEMORY CELL A2 2048 ARRAY A1 2048 11 A0 BANK 0 ROW BA0 ROW ADDRESS ADDRESS BA1 LATCH BUFFER 11 11 SENSE AMP I/O GATE 256 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 2 Integrated Silicon Solution, Inc. www.issi.com Rev. A2 10/16/2019 MULTIPLEXER ROW DECODER