IS42S32400F IS45S32400F 4M x 32 128Mb SYNCHRONOUS DRAM NOVEMBER 2015 OVERVIEW FEATURES ISSI s 128Mb Synchronous DRAM achieves high-speed Clock frequency: 166, 143, 133 MHz data transfer using pipeline architecture. All inputs and Fully synchronous all signals referenced to a outputs signals refer to the rising edge of the clock input. positive clock edge The 128Mb SDRAM is organized in 1Meg x 32 bit x 4 Banks. Inter nal bank for hiding row access/precharge Single Power supply: 3.3V + 0.3V KEY TIMING PARAMETERS LVTTL interface Programmable burst length Parameter -6 -7 -75E Unit (1, 2, 4, 8, full page) Clk Cycle Time CAS Latency = 3 6 7 ns Programmable burst sequence: CAS Latency = 2 10 10 7.5 ns Sequential/Interleave Clk Frequency Auto Refresh (CBR) CAS Latency = 3 166 143 Mhz CAS Latency = 2 100 100 133 Mhz Self Refresh Access Time from Clock 4096 refresh cycles ever y 16ms (A2 grade) or CAS Latency = 3 5.4 5.4 ns 64 ms (Commercial, Industr ial, A1 grade) CAS Latency = 2 6.5 6.5 5.5 ns Random column address ever y clock cycle Programmable CAS latency (2, 3 clocks) Burst read/wr ite and burst read/single wr ite ADDRESS TABLE operations capability Parameter 4M x 32 Burst ter mination by burst stop and precharge command Configuration 1M x 32 x 4 banks Refresh Count Com./Ind. 4K / 64ms OPTIONS A1 4K / 64ms Package: 86-pin TSOP-II A2 4K / 16ms 90-ball TF-BGA Row Addresses A0 A11 Operating Temperature Range: Column A0 A7 o o Commercial (0 C to +70 C) Addresses o o Industr ial (-40 C to +85 C) Bank Address BA0, BA1 o o Automotive Grade, A1 (-40 C to +85 C) Pins o o Automotive Grade, A2 (-40 C to +105 C) Autoprecharge A10/AP Pins Copyright 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such ap- plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. - www.issi.com 1 Rev. D 10/28/2015IS42S32400F, IS45S32400F DEVICE OVERVIEW A self-timed row precharge initiated at the end of the burst The 128Mb SDRAM is a high speed CMOS, dynamic sequence is available with the AUTO PRECHARGE function random-access memor y designed to operate in 3.3V Vdd enabled. Precharge one bank while accessing one of the and 3.3V Vddq memor y systems containing 134,217,728 other three banks will hide the precharge cycles and provide bits. Inter nally configured as a quad-bank DRAM with a seamless, high-speed, random-access operation. synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 256 columns by 32 bits. SDRAM read and write accesses are burst oriented starting at a selected location and continuing for a programmed The 128Mb SDRAM includes an AUTO REFRESH MODE, number of locations in a programmed sequence. The and a power-saving, power-down mode. All signals are registration of an ACTIVE command begins accesses, registered on the positive edge of the clock signal, CLK. followed by a READ or WRITE command. The ACTIVE All inputs and outputs are LVTTL compatible. command in conjunction with address bits registered are The 128Mb SDRAM has the ability to synchronously burst used to select the bank and row to be accessed (BA0, data at a high data rate with automatic column-address BA1 select the bank A0-A11 select the row). The READ generation, the ability to interleave between internal banks or WRITE commands in conjunction with address bits to hide precharge time and the capability to randomly registered are used to select the starting column location change column addresses on each clock cycle during for the burst access. burst access. Programmable READ or WRITE burst lengths consist of 1, 2, 4 and 8 locations or full page, with a burst ter minate option. FUNCTIONAL BLOCK DIAGRAM (FOR 1MX32X4 BANKS) CLK DQM0 - DQM3 CKE COMMAND DATA IN CS 4 DECODER BUFFER RAS 32 32 & CAS CLOCK WE REFRESH MODE DQ 0-31 GENERATOR CONTROLLER REGISTER 12 VDD/VDDQ SELF DATA OUT REFRESH A10 BUFFER Vss/VssQ CONTROLLER 32 32 A11 A9 A8 A7 REFRESH A6 COUNTER A5 A4 4096 A3 4096 MEMORY CELL A2 4096 ARRAY A1 4096 12 A0 BANK 0 ROW ROW BA0 ADDRESS ADDRESS BA1 LATCH BUFFER 12 12 SENSE AMP I/O GATE 256 (x 32) COLUMN BANK CONTROL LOGIC ADDRESS LATCH 8 BURST COUNTER COLUMN DECODER COLUMN ADDRESS BUFFER 8 2 Integrated Silicon Solution, Inc. - www.issi.com Rev. D 10/28/2015 MULTIPLEXER ROW DECODER