IS43/46DR81280B(L), IS43/46DR16640B(L) MARCH 2015 1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz SSTL 18 interface 8 internal banks for concurrent operation tRAS lockout supported 4-bit prefetch architecture Operating temperature: Commercial (T = 0C to 70C T = 0C to 85C) Programmable CAS Latency: 3, 4, 5, 6 and 7 A C Industrial (T = -40C to 85C T = -40C to 95C) A C Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Automotive, A1 (T = -40C to 85C T = -40C to 95C) A C Write Latency = Read Latency-1 Automotive, A2 (T = -40C to 105C T = -40C to A C 105C) Programmable Burst Sequence: Sequential or Interleave OPTIONS Programmable Burst Length: 4 and 8 Configuration: Automatic and Controlled Precharge Command 128Mx8 (16M x 8 x 8 banks) Power Down Mode 64Mx16 (8M x 16 x 8 banks) Auto Refresh and Self Refresh Package: Refresh Interval: 7.8 s (8192 cycles/64 ms) 60-ball TW-BGA for x8 ODT (On-Die Termination) 84-ball TW-BGA for x16 Weak Strength Data-Output Driver Option Self-Refresh: Bidirectional differential Data Strobe (Single- Standard ended data-strobe is an optional feature) Low Power (L) On-Chip DLL aligns DQ and DQs transitions with CK transitions ADDRESS TABLE DQS can be disabled for single-ended data strobe Parameter 128Mx8 64Mx16 Row Addressing A0-A13 A0-A12 Read Data Strobe supported (x8 only) Column Addressing A0-A9 A0-A9 Differential clock inputs CK and CK Bank Addressing BA0-BA2 BA0-BA2 VDD and VDDQ = 1.8V 0.1V Precharge Addressing A10 A10 PASR (Partial Array Self Refresh) Clock Cycle Timing -3D -25E -25D Units Speed Grade DDR2-667D DDR2-800E DDR2-800D CL-tRCD-tRP 5-5-5 6-6-6 5-5-5 tCK tCK (CL=3) 5 5 5 ns tCK (CL=4) 3.75 3.75 3.75 ns tCK (CL=5) 3 3 2.5 ns tCK (CL=6) 3 2.5 2.5 ns tCK (CL=7) 3 2.5 2.5 ns Frequency (max) 333 400 400 MHz Copyright 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Rev. G 1 3/25/2015 IS43/46DR81280B(L), IS43/46DR16640B(L) Package Ball-out and Description DDR2 SDRAM (128Mx8) TW-BGA Ball-out (Top-View) (8.00mm x 10.50mm) Symbol Description Notes: 1. Pins B3 and A2 have identical capacitance as pins B7 CK, CK Input clocks and A8. CKE Clock enable 2. For a read, when enabled, strobe pair RDQS & RDQS CS Chip Select are identical in function and timing to strobe pair DQS & RAS ,CAS ,WE DQS and input masking function is disabled. Command control pins 3. The function of DM or RDQS/RDQS are enabled by A 13:0 Address EMRS command. BA 2:0 Bank Address 4. VDDL and VSSDL are power and ground for the DLL. DQ 7:0 I/O DQS, DQS Data Strobe RDQS, RDQS Redundant Data Strobe DM Input data mask VDD Supply voltage VSS Ground VDDQ DQ power supply VSSQ DQ ground VREF Reference voltage VDDL DLL power supply VSSDL DLL ground ODT On Die Termination Enable NC No connect Rev. G 2 3/25/2015