IS43DR32800A, IS43/46DR32801A 8Mx32 PRELIMINARYINFORMA TION 256MbDDR2DRAM SEPTEMBER2010 FEATURES DESCRIPTION ISSI s 256Mb DDR2 SDRAM uses a double-data-rate Vdd = 1.8V 0.1VV,ddq = 1.8V 0.1V architecture to achieve high-speed operation. The JEDEC standard 1.8V I/O (SSTL 18-compatible) double-data rate architecture is essentially a 4n-prefetch Double data rate interface: two data transfers architecture, with an interface designed to transfer two per clock cycle data words per clock cycle at the I/O balls. Differential data strobe (DQS, DQS) The 256Mb DDR2 SDRAM is provided in a wide bus 4-bit prefetch architecture x32 format, designed to offer a smaller footprint and support compact designs. On chip DLL to align DQ and DQS transitions with CK ADDRESS TABLE 4 internal banks for concurrent operation Parameter 8M x 32 8M x 32 Programmable CAS latency (CL) 3, 4, 5, and 6 Standard Page Reduced Page supported Size Option Size Option Posted CAS and programmable additive latency Configuration 2M x 32 x 4 banks 2M x 32 x 4 banks (AL) 0, 1, 2, 3, 4, and 5 supported Refresh Count 4K/64ms 8K/64ms WRITE latency = READ latency - 1 tCK Row Addressing A0-A11 A0-A12 Programmable burst lengths: 4 or 8 Column A0-A8 A0-A7 Addressing Adjustable data-output drive strength, full and reduced strength options Bank Addressing BA0, BA1 BA0, BA1 Precharge A10/AP A10/AP On-die termination (ODT) Addressing OPTIONS Configuration: 8M x 32 (IS43DR32800A Standard Page - 4K refresh) 8M x 32 (IS43/46DR32801A Reduced Page - 8K KEY TIMINGPARAMETERS refresh) Package: x32: 126WBGA SpeedGrade -37C -5B Timing Cycle time tRCD 15 15 3.0ns CL=5, DDR2-667D tRP 15 15 3.75ns CL=4, DDR2-533C tRC 60 55 5.0ns CL=3, DDR2-400B tRAS 45 40 Temperature Range: tCK CL=3 5 5 Commercial (0C Tc 85C 0C Ta 70C) tCK CL=4 3.75 5 Industrial (40C Tc 95C 40C Ta 85C) Automotive, A1 (40C Tc 95C 40C Ta 85C) tCK CL=5 3.75 5 Automotive, A2 (40C Tc 105C 40C Ta 105C) tCK CL=6 3.75 5 Tc = CaseTemp , Ta = AmbientTemp Copyright 2010 Integrated Silicon Solution, Inc.All rights reserv ed.ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services descrCustomersibed herein. are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason- ably be expected to cause failure of the life support system or to significantly affect its safety or effProductsectiveness are. not authorized for use in such applications unless Integrated Silicon Solution, Inc.receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. www.issi.com 1 Rev. 00E 09/08/2010IS43DR32800A, IS43/46DR32801A GENERALDESCRIPTION Read and write accesses to the DDR2 SDRAM are burst oraccessesiented start at a selected location and continue for a burst length of four or eight in a programmed sequence Accesses. begin with the registration of an Active command, which is then followed by a ReadWrite or command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA1 select A0-A11/A12 the bank select the row and A0-A7/A8 select the column). The address bits registered coincident with the ReadWrite or command are used to select the starting column location for the burst access and to determine if the auto precharge command is to be issued. Prior to normal operation, the DDR2 SDRAM must be initializ The ed.following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. FUNCTIONALBLOCKDIAGRAM CK CK CKE COMMAND DECODER ODT & CS CLOCK REFRESH DQ0 DQ31 RAS GENERATOR CONTROLLER CAS DLL WE SELF REFRESH CONTROLLER ODT CIRCUIT MODE REGISTERS REFRESH MEMORY CELL COUNTER ARRAY MEMORY CELL ARRABYANK 0 BANK 0 ROW OUTPUT INPUT A0 An, ADDRESS DATA DATA BA0 BA1 BUFFER BUFFER LATCH ROW SENSE AMP ADDRESS BUFFER SENSE AMP DM0 DM3 I/O GATE BANK CONTROL LOGIC & MASK LOGIC COLUMN DATA ADDRESS LATCH DQS0 DQS3, STROBE COLUMN DECODER COLUMN DECODER GENERATOR DQS0 DQS3 COLUMN DECODER COLUMN DECODER BURST COUNTER COLUMN ADDRESS BUFFER Notes: 1.) An: n = no. of address pins 1 2 Integrated Silicon Solution, Inc. www.issi.com Rev. 00E 09/08/2010 MULTIPLEXER ROW DECODER ROW DECODER