IS49NLC96400A/IS49NLC18320A/IS49NLC36160A 64Mbx9, 32Mbx18, 16Mbx36 JUNE 2021 Common I/O RLDRAM 2 Memory FEATURES 533MHz DDR operation (1.067 Gb/s/pin data rate) Differential input clocks (CK, CK ) 38.4Gb/s peak bandwidth (x36 at 533 MHz clock Differential input data clocks (DKx, DKx ) frequency) On-die DLL generates CK edge-aligned data and Reduced cycle time (15ns at 533MHz) output data clock signals 32ms refresh (16K refresh for each bank 128K Data valid signal (QVLD) refresh command must be issued in total each 32ms) HSTL I/O (1.5V or 1.8V nominal) 8 internal banks 25-60 matched impedance outputs Non-multiplexed addresses (address multiplexing 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O option available) On-die termination (ODT) RTT SRAM-type interface IEEE 1149.1 compliant JTAG boundary scan Programmable READ latency (RL), row cycle time, Operating temperature: and burst sequence length Commercial Balanced READ and WRITE latencies in order to (T = 0 to +95C ) C optimize data bus utilization Industrial Data mask signals (DM) to mask signal of WRITE (TC = -40C to +95C TA = -40C to +85C) data DM is sampled on both edges of DK. OPTIONS Package: 144-ball WBGA (lead-free) Configuration: 64Mx9 32Mx18 16Mx36 Clock Cycle Timing: Speed Grade -18 -25E -25 -33 Unit t 15 15 20 20 ns RC t 1.875 2.5 2.5 3.3 ns CK Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances RLDRAM is a registered trademark of Micron Technology, Inc. Integrated Silicon Solution, Inc. www.issi.com 1 Rev.A3, 06/21/2021 IS49NLC96400A/IS49NLC18320A/IS49NLC36160A 1 Package Ball out and Description 1.1 576Mb (64Mx9) Common I/O BGA Ball-out (Top View) 12 1 2 3 4 5 6 7 8 9 10 11 V V V V V V TMS TCK REF SS EXT SS SS EXT A 3 3 3 V DNU DNU V V DQ0 DNU V DD SSQ SSQ DD B 3 3 3 V DNU DNU V V DQ1 DNU V TT DDQ DDQ TT C 1 3 3 A22 DNU DNU V V QK0 QK0 V SSQ SSQ SS D 3 3 3 A21 DNU DNU V V DQ2 DNU A20 DDQ DDQ E 3 3 3 A5 DNU DNU V V DQ3 DNU QVLD SSQ SSQ F A8 A6 A7 V V A2 A1 A0 DD DD G BA2 A9 V V V V A4 A3 SS SS SS SS H 2 2 NF NF V V V V BA0 CK DD DD DD DD J DK DK V V V V BA1 CK DD DD DD DD K REF CS V V V V A14 A13 SS SS SS SS L WE A16 A17 V V A12 A11 A10 DD DD M 3 3 3 A18 DNU DNU V V DQ4 DNU A19 SSQ SSQ N 3 3 3 A15 DNU DNU V V DQ5 DNU DM P DDQ DDQ 3 3 3 VSS DNU DNU VSSQ VSSQ DQ6 DNU VSS R 3 3 3 V DNU DNU V V DQ7 DNU V T TT DDQ DDQ TT 3 3 3 VDD DNU DNU VSSQ VSSQ DQ8 DNU VDD U V ZQ V V V V TD0 TDI V REF EXT SS SS EXT Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins are High-Z. Integrated Silicon Solution, Inc. www.issi.com 2 Rev.A3, 06/21/2021