IS49NLC93200,IS49NLC18160,IS49NLC36800 288Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory DECEMBER 2012 FEATURES 400MHz DDR operation (800Mb/s/pin data rate) Differential input clocks (CK, CK ) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock Differential input data clocks (DKx, DKx ) frequency) On-die DLL generates CK edge-aligned data and Reduced cycle time (15ns at 400MHz) output data clock signals 32ms refresh (8K refresh for each bank 64K refresh Data valid signal (QVLD) command must be issued in total each 32ms) HSTL I/O (1.5V or 1.8V nominal) 8 internal banks 25-60 matched impedance outputs Non-multiplexed addresses (address multiplexing 2.5V V , 1.8V V , 1.5V or 1.8V V I/O EXT DD DDQ option available) On-die termination (ODT) R TT SRAM-type interface IEEE 1149.1 compliant JTAG boundary scan Programmable READ latency (RL), row cycle time, Operating temperature: and burst sequence length Commercial Balanced READ and WRITE latencies in order to (T = 0 to +95C T = 0C to +70C), C A optimize data bus utilization Industrial Data mask signals (DM) to mask signal of WRITE (T = -40C to +95C T = -40C to +85C) C A data DM is sampled on both edges of DK. OPTIONS Package: 144-ball FBGA (leaded) 144-ball FBGA (lead-free) Configuration: 32Mx9 16Mx18 8Mx36 Clock Cycle Timing: Speed Grade -25E -25 -33 -5 Unit t 15 20 20 20 ns RC t 2.5 2.5 3.3 5 ns CK Copyright 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances RLDRAM is a registered trademark of Micron Technology, Inc. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. 00I, 12/10/2012 IS49NLC93200,IS49NLC18160,IS49NLC36800 1 Package Ballout and Description 1.1 288Mb (32Mx9) Common I/O BGA Ball-out (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A VREF VSS VEXT VSS VSS VEXT TMS TCK 4 4 4 B VDD DNU DNU VSSQ VSSQ DQ0 DNU VDD 4 4 4 C VTT DNU DNU VDDQ VDDQ DQ1 DNU VTT 1 4 4 D A22 DNU DNU VSSQ VSSQ QK0 QK0 VSS 2 4 4 4 E A21 DNU DNU VDDQ VDDQ DQ2 DNU A20 4 4 4 F A5 DNU DNU VSSQ VSSQ DQ3 DNU QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 3 3 J NF NF VDD VDD VDD VDD BA0 CK K DK DK VDD VDD VDD VDD BA1 CK L REF CS VSS VSS VSS VSS A14 A13 M WE A16 A17 VDD VDD A12 A11 A10 4 4 4 N A18 DNU DNU VSSQ VSSQ DQ4 DNU A19 4 4 4 P A15 DNU DNU VDDQ VDDQ DQ5 DNU DM 4 4 4 R VSS DNU DNU VSSQ VSSQ DQ6 DNU VSS 4 4 4 T VTT DNU DNU VDDQ VDDQ DQ7 DNU VTT 4 4 4 U VDD DNU DNU VSSQ VSSQ DQ8 DNU VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Symbol Description Ball count Notes: NONOTTEES:S: 1. Reserved for future use. This signal is not connected. VDD Supply voltage 16 11)) ReservReserved ed ffoor r ffutureuture ususe.e. TThishis mmaayy 2.Reserved for future use. This signal is internally VSS Ground 16 ooptioptionanallylly be be coconnnnecectted ed ttoo GGND.ND. connected and has parasitic characteristics of an address VDDQ DQ power supply 8 22)) ReservReserved ed ffoor r ffutureuture ususe.e. TThishis ssigignanal is l is input signal. inteinternarnallylly coconnnnecectted ed aandnd hahass papararassititic ic 3. No function. This signal is internally connected and has VSSQ DQ Ground 12 parasitic characteristics of a clock input signal. This may chachararactctererisisttics ics ooff aan an addddreressss inpinput ut ssigignanal. l. VEXT Supply voltage 4 optionally be connected to GND. TThishis mmaayy ooptioptionanallylly be be coconnnnecectted ed ttoo GGND.ND. VREF Reference voltage 2 4. Do not use. This signal is internally connected and has 3) No function. This signal is internally VTT Termination voltage 4 parasitic characteristics of a I/O. This may optionally be connected and has parasitic characteristics connected to GND. Note that if ODT is enabled, these A* Address - A0-22 23 of a clock input signal. This may optionally pins are High-Z. BA* Banks - BA0-2 3 be connected to GND. DQ* I/O 9 4) Do not use. This signal is internally DK* Input data clock(Differential inputs) 2 connected and has parasitic characteristics QK* Output data clocks(outputs) 2 of a I/O. This may optionally be connected CK* Input clocks (CK, CK ) 2 to GND. Note that if ODT is enabled, these DM Input data mask 1 pins will be connected to VTT. CS ,WE ,REF Command control pins 3 ZQ External impedance (2560) 1 QVLD Data valid 1 DNU,NF Do not use, No function 31 T* JTAG - TCK,TMS,TDO,TDI 4 Total 144 Integrated Silicon Solution, Inc. www.issi.com 2 Rev. 00I, 12/10/2012