IS49NLS96400A, IS49NLS18320A 576Mb (64Mbx9, 32Mbx18) JUNE 2021 Separate I/O RLDRAM 2 Memory FEATURES 533MHz DDR operation (1.067 Gb/s/pin data rate) Differential input clocks (CK, CK ) 38.4Gb/s peak bandwidth (x18 at 533 MHz clock Differential input data clocks (DKx, DKx ) frequency) On-die DLL generates CK edge-aligned data Reduced cycle time (15ns at 533MHz) and output data clock signals 32ms refresh (16K refresh for each bank 128K Data valid signal (QVLD) refresh command must be issued in total each HSTL I/O (1.5V or 1.8V nominal) 32ms) 25-60 matched impedance outputs 8 internal banks 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O Non-multiplexed addresses (address On-die termination (ODT) R TT multiplexing option available) IEEE 1149.1 compliant JTAG boundary scan SRAM-type interface Operating temperature: Programmable READ latency (RL), row cycle Commercial time, and burst sequence length (T = 0 to +95C) C Balanced READ and WRITE latencies in order Industrial to optimize data bus utilization (T = -40C to +95C T = -40C to +85C) C A Data mask signals (DM) to mask signal of WRITE data DM is sampled on both edges of DK. OPTIONS Package: 144-ball WBGA (lead-free) Configuration: 64Mx9 32Mx18 Clock Cycle Timing: Speed Grade -18 -25E -25 -33 Unit t 15 15 20 20 ns RC t 1.875 2.5 2.5 3.3 ns CK Copyright 2021 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances RLDRAM is a registered trademark of Micron Technology, Inc. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. A1, 06/21/2021 IS49NLS96400A, IS49NLS18320A 1 Package Ballout and Description 1.1 576Mb (64Mx9) Separate I/O BGA Ball-out (Top View) 12 1 2 3 4 5 6 7 8 9 10 11 VREF VSS VEXT VSS VSS VEXT TMS TCK A 3 3 VDD DNU DNU VSSQ VSSQ Q0 D0 VDD B 3 3 V DNU DNU V V Q1 D1 V TT DDQ DDQ TT C 1 3 3 A22 DNU DNU VSSQ VSSQ QK0 QK0 VSS D 3 3 A21 DNU DNU VDDQ VDDQ Q2 D2 A20 E 3 3 A5 DNU DNU V V Q3 D3 QVLD SSQ SSQ F A8 A6 A7 VDD VDD A2 A1 A0 G BA2 A9 VSS VSS VSS VSS A4 A3 H 2 2 NF NF V V V V BA0 CK DD DD DD DD J DK DK VDD VDD VDD VDD BA1 CK K REF CS VSS VSS VSS VSS A14 A13 L WE A16 A17 V V A12 A11 A10 DD DD M 3 3 A18 DNU DNU VSSQ VSSQ Q4 D4 A19 N 3 3 A15 DNU DNU VDDQ VDDQ Q5 D5 DM P 3 3 V DNU DNU V V Q6 D6 V R SS SSQ SSQ SS 3 3 VTT DNU DNU VDDQ VDDQ Q7 D7 VTT T 3 3 V DNU DNU V V Q8 D8 V U DD SSQ SSQ DD VREF ZQ VEXT VSS VSS VEXT TD0 TDI V Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to GND. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND. Note that if ODT is enabled, these pins are High-Z. Integrated Silicon Solution, Inc. www.issi.com 2 Rev. A1, 06/21/2021