IS49NLS93200,IS49NLS18160 288Mb (x9, x18) Separate I/O RLDRAM 2 Memory JANUARY 2020 FEATURES 400MHz DDR operation (800Mb/s/pin data rate) Differential input clocks (CK, CK ) 14.4 Gb/s peak bandwidth (x18 Separate I/O at 400 Differential input data clocks (DKx, DKx ) MHz clock frequency) On-die DLL generates CK edge-aligned data and Reduced cycle time (15ns at 400MHz) output data clock signals 32ms refresh (8K refresh for each bank 64K refresh Data valid signal (QVLD) command must be issued in total each 32ms) HSTL I/O (1.5V or 1.8V nominal) 8 internal banks 25-60 matched impedance outputs Non-multiplexed addresses (address multiplexing 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O option available) On-die termination (ODT) RTT SRAM-type interface IEEE 1149.1 compliant JTAG boundary scan Programmable READ latency (RL), row cycle time, Operating temperature: and burst sequence length Commercial Balanced READ and WRITE latencies in order to (TC = 0 to +95C TA = 0C to +70C), optimize data bus utilization Industrial Data mask signals (DM) to mask signal of WRITE (T = -40C to +95C T = -40C to +85C) C A data DM is sampled on both edges of DK. OPTIONS Package: 144-ball WBGA (lead-free) Configuration: 32Mx9 16Mx18 Clock Cycle Timing: Speed Grade -25E -25 -33 Unit t 15 20 20 ns RC t 2.5 2.5 3.3 ns CK Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances RLDRAM is a registered trademark of Micron Technology, Inc. Integrated Silicon Solution, Inc. www.issi.com 1 Rev. B, 01/22/2020 IS49NLS93200,IS49NLS18160 1 Package Ballout and Description 1.1 288Mb (32Mx9) Separate I/O BGA Ball-out (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A VREF VSS VEXT VSS VSS VEXT TMS TCK 3 3 B VDD DNU DNU VSSQ VSSQ Q0 D0 VDD 3 3 C VTT DNU DNU VDDQ VDDQ Q1 D1 VTT 1 3 3 D A22 DNU DNU VSSQ VSSQ QK0 QK0 VSS 1 3 3 E A21 DNU DNU VDDQ VDDQ Q2 D2 A20 3 3 F A5 DNU DNU VSSQ VSSQ Q3 D3 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 2 2 J NF NF VDD VDD VDD VDD BA0 CK K DK DK VDD VDD VDD VDD BA1 CK L REF CS VSS VSS VSS VSS A14 A13 M WE A16 A17 VDD VDD A12 A11 A10 3 3 N A18 DNU DNU VSSQ VSSQ Q4 D4 A19 3 3 P A15 DNU DNU VDDQ VDDQ Q5 D5 DM 3 3 R VSS DNU DNU VSSQ VSSQ Q6 D6 VSS 3 3 T VTT DNU DNU VDDQ VDDQ Q7 D7 VTT 3 3 U VDD DNU DNU VSSQ VSSQ Q8 D8 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Notes: Symbol Description Ball count NNOOTTEESS:: 1. Reserved for future use. This may optionally be VDD Supply voltage 16 11)) RReeseserrvveedd ffoorr ffuuttuurree uusese.. TThhiis s mmaayy connected to GND. ooppttiioonnaallllyy bbee ccoonnnneecctteedd ttoo GGNNDD.. VSS Ground 16 2. No function. This signal is internally connected and 22)) RReeseserrvveedd ffoorr ffuuttuurree uusese.. TThhiis s sisiggnnaall iis s VDDQ DQ power supply 8 has parasitic characteristics of a clock input signal. iTinnhttisee mrrnnaaay llollpyyt iccooonnnalnnlyee bccettee cddo naannneddct ehhdaa ts s o ppGNaarrDaa. sisittiicc VSSQ DQ Ground 12 3. Do not use. This signal is internally connected and cchhaarraacctteerriiststiiccs s ooff aann aaddddrreessss iinnppuutt sisiggnnaall.. VEXT Supply voltage 4 has parasitic characteristics of a I/O. This may TThhiis s mmaayy ooppttiioonnaallllyy bbee ccoonnnneecctteedd ttoo VREF Reference voltage 2 optionally be connected to GND. Note that if ODT is GGNNDD.. enabled, these pins are High-Z. VTT Termination voltage 4 3) No function. This signal is internally A* Address - A0-22 23 connected and has parasitic BA* Banks - BA0-2 3 characteristics of a clock input signal. D* Input data 9 This may optionally be connected to GND. Q* Output data 9 4) Do not use. This signal is internally DK* Input data clock(Differential inputs) 2 connected and has parasitic QK* Output data clocks(outputs) 2 characteristics of a I/O. This may CK* Input clocks (CK, CK ) 2 optionally be connected to GND. Note DM Input data mask 1 that if ODT is enabled, these pins will be CS ,WE ,REF Command control pins 3 connected to VTT. ZQ External impedance (2560) 1 QVLD Data valid 1 DNU,NF Do not use, No function 22 T* JTAG - TCK,TMS,TDO,TDI 4 Total 144 Integrated Silicon Solution, Inc. www.issi.com 2 Rev. B, 01/22/2020