IS66WVH16M8ALL/BLL IS67WVH16M8ALL/BLL 16M x 8 HyperRAM 6(37(0%(5 2018 Overview The IS66/67WVH16M8ALL/BLL are integrated memory device of 128Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 16M words by 8 bits. The device is a dual die stack of two 64Mb die. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications. Distinctive Characteristics TM High Performance HyperBus Low Signal Count Interface 3.0V I/O, 11 bus signals Up to 333MB/s Single ended clock (CK) Double-Data Rate (DDR) - two data transfers per clock 1.8V I/O, 12 bus signals 166-MHz clock rate (333 MB/s) at 1.8V V CC Differential clock (CK, CK ) 100-MHz clock rate (200 MB/s) at 3.0V V CC Chip Select (CS ) Sequential burst transactions 8-bit data bus (DQ 7:0 ) Configurable Burst Characteristics Read-Write Data Strobe (RWDS) Wrapped burst lengths: Bidirectional Data Strobe / Mask 16 bytes (8 clocks) Output at the start of all transactions to indicate refresh 32 bytes (16 clocks) latency 64 bytes (32 clocks) Output during read transactions as Read Data Strobe 128 bytes (64 clocks) Input during write transactions as Write Data Mask Linear burst RWDS DCARS Timing Hybrid option - one wrapped burst followed by linear burst During read transactions RWDS is offset by a second Wrapped or linear burst type selected in each transaction clock, phase shifted from CK Configurable output drive strength The Phase Shifted Clock is used to move the RWDS Package transition edge within the read data eye 24-ball FBGA Performance Summary Read Transaction Timings Maximum Current Consumption Maximum Clock Rate at 1.8V V /V Q 166 MHz Burst Read or Write (linear burst at 166 MHz, 3V) 45 mA CC CC Maximum Clock Rate at 3.0V V /V Q 100 MHz Burst Read or Write (linear burst at 166 MHz, 1.8V) 60 mA CC CC Maximum Access Time, (t at 166 MHz) 36 ns Standby (CS = High, 3V, 105 C) 600 A ACC Maximum CS Access Time to first word at Standby (CS = High, 1.8V, 105 C) 600 A 56 ns 166 MHz (excluding refresh latency) Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev.B4 09/21/2018IS66WVH16M8ALL/BLL IS67WVH16M8ALL/BLL Block Diagram RWDS RWDS DQ0~DQ7 DQ0~DQ7 VssQ VssQ VccQ VccQ RESET RESET 64Mb CS CS HyperRAM Vss Vss (Top Die) CK/CK CK/CK (PSC/PSC ) (PSC/PSC ) Vcc Vcc RWDS DQ0~DQ7 VssQ VccQ RESET 64Mb CS HyperRAM Vss (Bottom Die) CK/CK (PSC/PSC ) Vcc Key Diefference between Stacked 128Mb and Monolithic 64Mb Stacked 128Mb device is different from monolithic based 64Mb in below 6 items. 1. Configuration Register 0, 1 must be set per each die individually by CA35 (0 or 1). CA35 (A22) = 0 for bottom die, CA35 (A22) = 1 for top die. 2. Deep Power Down mode by CR write supports for only 1 die only ( either bottom or top die) It is selected by CA35 staus when Deep Power Down operation is executed. 3. Fixed Latency mode only supported (No Variable latency mode) 4. Table 5.1 ID Register Bit Assignments 5. When Linear Burst is selected by CA 45 , the device cannot advance across to next die. 6. Input Output Capacitance value will be doubled in stacked 128Mb device, which will impact on clock to data (strobe) access time of tCKD, tCKDI, tCKDS, tDSV and tID/tIH. Symbol Parameter 1.8V Device 3.0V Device tCKD CK transition to DQ Valid 5.5ns 6.5ns 7.0ns 8.0ns 4.6/4.5/4.3ns tCKDI CK transition to RWDS Valid 5.2ns 6.2ns 5. 6/5.5/5.3ns tCKDS CK transition to RWDS Valid 5.5ns 6.5ns 7.0ns 8.0ns tDSV Data Strobe Valid 12.0ns 13.0ns 12.0ns 13.0ns 0.6/0.8/1.0ns tIS/tIH Input Setup/Hold No change (1.0ns) 0. 9/0.9/1.0ns Integrated Silicon Solution, Inc.- www.issi.com 2 Rev.B4 09/21/2018