IS66WVH32M8DALL/BLL IS67WVH32M8DALL/BLL 32M x 8 HyperRAM SEPTEMBER 2020 Overview The IS66/67WVH32M8DALL/BLL are integrated memory device containing 256Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 32M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed specially for Mobile and Automotive applications. Distinctive Characteristics TM High Performance HyperBus Low Signal Count Interface 3.0V I/O, 11 bus signals Up to 400MB/s Single ended clock (CK) Double-Data Rate (DDR) - two data transfers per clock 1.8V I/O, 12 bus signals 200-MHz clock rate (400 MB/s) at 1.8V V CC Differential clock (CK, CK ) 166-MHz clock rate (332 MB/s) at 3.0V V CC Chip Select (CS ) Sequential burst transactions 8-bit data bus (DQ 7:0 ) Configurable Burst Characteristics Read-Write Data Strobe (RWDS) Wrapped burst lengths: Bidirectional Data Strobe / Mask 16 bytes (8 clocks) Output at the start of all transactions to indicate refresh 32 bytes (16 clocks) latency 64 bytes (32 clocks) Output during read transactions as Read Data Strobe 128 bytes (64 clocks) Input during write transactions as Write Data Mask Linear burst RWDS DCARS Timing Hybrid option - one wrapped burst followed by linear burst During read transactions RWDS is offset by a second Wrapped or linear burst type selected in each transaction clock, phase shifted from CK Configurable output drive strength The Phase Shifted Clock is used to move the RWDS Temperature Grade transition edge within the read data eye Industrial: -40C to +85C Auto (A1) Grade: -40C to +85C Auto (A2) Grade: -40C to +105C Package 24-ball FBGA Performance Summary Read Transaction Timings Maximum Current Consumption Maximum Clock Rate at 1.8V V /V Q 200 MHz Burst Read (linear burst at 200 MHz, 1.8V, 105 C) 40mA CC CC Maximum Clock Rate at 3.0V V /V Q 166 MHz Burst Write (linear burst at 200 MHz, 1.8V, 105 C) 35 mA CC CC Maximum Access Time, (t at 200 MHz) 40 ns Standby (CS = High, 3V, 105 C) 1200 A ACC Deep Power Down (CS = High, 3V, 105 C) 50 A Standby (CS = High, 1.8V, 105 C) 1200 A Deep Power Down (CS = High, 1.8V, 105 C) 30 A Copyright 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized b.) the user assume all such risks and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc.- www.issi.com 1 Rev A 09/15/2020IS66WVH32M8DALL/BLL IS67WVH32M8DALL/BLL Logic Block Diagram CS Memory CK/CK (PSC/PSC ) Control Y Decoders RWDS I/O Logic Data Latch DQ 7:0 RESET Data Path Integrated Silicon Solution, Inc.- www.issi.com 2 Rev A 09/15/2020 X Decoders