CPC5622-EVAL-600R LITELINK III Evaluation Board INTEGRATED CIRCUITS DIVISION Users Guide 1. Introduction Thank you for using IXYS IC Divisions Figure 2. Evaluation Board Bottom View CPC5622-EVAL-600R evaluation board. The evaluation board ships with the CPC5622A LITELINK III and CPC5712U Voltage Monitor to demonstrate the functionality of a PSTN terminating two-wire interface that provides both the analog voice transmission and signaling functions. The analog interface is configured to provide a 600 resistive AC impedance with 0dB gain in both the transmit and receive directions. While the CPC5622A provides the hook-switch and ringing detect signaling functions, the CPC5712U is utilized to monitor and detect changes in the DC line voltage to determine loop status and signaling information sent by the network. Loop status is given by the logic level outputs of the three CPC5712U on-board detectors indicating Loop The printed-circuit board used for the Presence, Line In Use, and Loop Polarity. CPC5622-EVAL-600R evaluation board is a multi-purpose board that facilitates prototyping of CPC5622-EVAL-600R evaluation board top and many PSTN line interface configurations by simple bottom views are shown in the following illustrations. component changes. Specific evaluation board models provided by IXYS IC Division can be identified Figure 1. Evaluation Board Top View by the label appended to the core part number CPC5622-EVAL-. The suffix label 600R as shown in Figure 1 for this model indicates the two-wire AC input impedance is 600. For the 600R model, the transmit and receive gains are 0dB. 600R = 600 resistive AC termination with 0dB transmit and receive gains. In addition to the model identification label some boards may have a second label located just below the evaluation board part number indicating the evaluation boards serial number. UG-CPC5622-EVAL-600R - Rev A www.ixysic.com 1LITELINK III Evaluation Board Users Guide INTEGRATED CIRCUITS DIVISION 2. Setup and Using the Evaluation Board This section describes setting up the CPC5622-EVAL-600R Evaluation Board prior to use. 2.1 Connections The CPC5622-EVAL-600R evaluation board uses two PSTN loop connections while J2, the 12-position pin 100 mil (2.54 mm) pitch pin headers, J1 and J2, for the header, provides access for the low voltage side input and output connections. IXYS IC recommends power, logic control, logic-level loop status detector constructing header jumpers to bring the connections outputs and the analog transmit and receive voice out to your development or test platform. Connector paths. J1, the two-position pin header, provides access to the Table 1: Telephone Network Access Connector - J1 Silk Schematic Pin Use Screen Name 1 1 RING Connect to the Ring (B) lead of the telephone network or a loop simulator. 2 TIP Connect to the Tip (A) lead of the telephone network or a loop simulator. Table 2: Low Voltage Side Power and Signal Connector - J2 Silk Schematic Pin Use Screen Name Power input: +3.3 V or +5 V 1V+ VCC DC DC 2 TX- TX- IN Inverting analog input to the LITELINK 3 TX+ TX+ IN Non-inverting analog input to the LITELINK 4 RX- RX- OUT Negative analog output from LITELINK 5 RX+ RX+ OUT Positive analog output from LITELINK 6 LOOP LOOP Loop Presence detector output 7 OH OH* Hook switch control. Off-Hook: OH* = 0, On-Hook: OH* = 1 8 RING2 RING2* Full-wave ringing detector output 9 RING RING* Half-wave ringing detector output 10 LIU LIU* Line In Use detector output 11 GND Low voltage side ground 12 POL POLARITY Polarity Detector output NOTE: For clarity and consistency with the schematic, the schematic names will be used from this point forward throughout the text. 2 www.ixysic.com UG-CPC5622-EVAL-600R - Rev A