CPC5750U IXYS

CPC5750 Single-Channel Voice Band CODEC INTEGRATED CIRCUITS DIVISION PRELIMINARY Features Description -law and A-law ITU G.711 Companding Codec The CPC5750 is a voice-band CODEC with Operates on +3.3V Power pin-selectable PCM or IOM-2 (GCI) digital interfaces. Differential Analog Signal Paths Clock frequencies for the PCM Mode range from Programmable Transmit and Receive Gain, +/-12dB 512kHz to 8.192MHz while the GCI interface allows in 0.1dB increments clocking at 2.048MHz and 4.096MHz. While the GCI Transmit Path 60Hz Rejection Filter interface utilizes the integrated data link to read and Differential amplifier drives +3.2dBm into 600 write the control registers, a four-wire Serial Peripheral Stable Gain over temperature Interface (SPI) bus provides register access while in PCM and IOM-2 GCI telecommunication interfaces PCM Mode. Short and Long Frame Syncs Supported The CODEC provides the necessary A/D and D/A Independent Transmit and Receive Programmable functions with pin-selectable -law or A-law Time Slots companding. A low-noise internal reference is used to Accepts PCLK from 512kHz to 8.192MHz keep signal gains well controlled over supply and SPI Serial Interface for control in PCM Mode temperature variations. Programmable gain of 12dB Programmable Power Down Mode, I = 20A DD for both transmit and receive allow the CPC5750 to Analog and Digital Loopback Modes for testing accept differential input signals as large as +8dBm, and to source +3.2dBm differential signals into 600 while operating from a single 3.3V supply. Ordering Information Part Description CPC5750U SSOP-24 Package 50/Tube CPC5750UTR SSOP-24 Package 2000/Reel CPC5750 Block Diagram SCLK V SDI DD Control SPI Register Interface SDO CS RST POR DLB A IN+ + ADC FIR -law/A-law A - IN- Filter Encoder V REF FS BAND GAP BUF D PCM/IOM-2 TX 0.22F Interface D V DD RX Logic V EE PCLK BUF SFSEL MUTE A OUT+ + FIR Noise m-law/A-law A - OUT- DAC Shaper Filter Decoder ALB DS-CPC5750-Rev F PRELIMINARY 1 D0 D1 D2 D3CPC5750 INTEGRATED CIRCUITS DIVISION PRELIMINARY 1. Specifications 3 1.1 Pinout 3 1.2 Pin Descriptions 3 1.3 Absolute Maximum Ratings . 4 1.4 Recommended Operating Conditions . 4 1.5 Specifications: General Conditions 4 1.6 Analog Interface Characteristics . 5 1.7 Digital Interface Characteristics 6 1.8 Transmit Path: Analog Inputs (A and A ) to Digital Output (D ) - AC Characteristics 7 IN+ IN- TX 1.9 Receive Path: Digital Input (D ) to Analog Outputs (A and A ) - AC Characteristics 8 RX OUT+ OUT- 1.10 Power Characteristics 9 1.11 Power-On Reset 9 2. Control Registers 10 2.1 Mode Control Register 11 2.2 TX Path Gain: 1dB Steps Register 12 2.3 TX Path Gain: +0.1dB Steps Register 12 2.4 RX Path Gain: 1dB Steps Register . 13 2.5 RX Path Gain: +0.1dB Steps Register 13 2.6 PCM Interface D Time Slot Assignment Register 13 RX 2.7 PCM Interface D Bit Delay Register 13 RX 2.8 PCM Interface D Time Slot Assignment Register 14 TX 2.9 PCM Interface D Bit Delay Register 14 TX 2.10 Reserved Register . 14 2.11 GPIO Control Register 14 3. Digital Transmission Modes: PCM or IOM-2 GCI 15 3.1 Digital Transmission Mode Selection . 15 3.2 PCLK Frequencies and Time Slot Selection . 15 3.3 Hardware Configuration For Transmission Mode Selection 16 4. Functional Description - To Do 17 5. PCM Bus Interface . 18 6. IOM-2 (GCI) Interface . 23 6.1 Monitor Channel Operations 25 7. 4-Wire SPI (Serial Peripheral Interface) . 33 7.1 Data Compression/Expansion 35 7.2 Power On Reset (POR) . 35 8. Manufacturing Information . 36 8.1 Moisture Sensitivity . 36 8.2 ESD Sensitivity 36 8.3 Reflow Profile . 36 8.4 Board Wash 36 8.5 Mechanical Dimensions . 37 Rev F PRELIMINARY 2