Memory Module Speci cations KVR13LSE9S8/4 4GB 1Rx8 512M x 72-Bit PC3L-10600 CL9 204-Pin ECC SODIMM DESCRIPTION SPECIFICATIONS This document describes ValueRAM s 512M x 72-bit (4GB) CL(IDD) 9 cycles DDR3L-1333 CL9 SDRAM (Synchronous DRAM), 1Rx8, ECC, Row Cycle Time (tRCmin) 49.5ns (min.) low voltage, memory module, based on nine 512M x 8-bit FBGA Refresh to Active/Refresh 260ns (min.) components. The SPD is programmed to JEDEC standard Command Time (tRFCmin) latency DDR3-1333 timing of 9-9-9 at 1.35V or 1.5V. This 204- Row Active Time (tRASmin) 36ns (min.) pin SODIMM uses gold contact fingers. The electrical and Maximum Operating Power (1.35V) = 1.761 W* mechanical specifications are as follows: (1.50V) = 1.957 W* UL Rating 94 V - 0 o o C to 85 C Operating Temperature 0 FEATURES o o Storage Temperature -55 C to +100 C JEDEC standard 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) Power Supply *Power will vary depending on the SDRAM. VDDQ = 1.35V (1.28V ~ 1.45V) and 1.5V (1.425V ~ 1.575V) 667MHz fCK for 1333Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 9, 8, 7, 6 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Thermal Sensor Grade B Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB: Height 1.18 (30mm), double sided component Continued >> Document No. VALUERAM1336-001.A00 04/23/13 Page 1 Document No. VALUERAM1336-001.A00 Page 2