Memory Module Speci cations KVR18R13D4K3/48 48GB (16GB 2Rx4 2G x 72-Bit x 3 pcs.) PC3-14900 CL13 Registered w/Parity 240-Pin DIMM Kit DESCRIPTION SPECIFICATIONS ValueRAM s KVR18R13D4K3/48 is a kit of three 2G x 72-bit CL(IDD) 13 cycles (16GB) DDR3-1866 CL13 SDRAM (Synchronous DRAM), Row Cycle Time (tRCmin) 47.125ns (min.) registered w/parity, 2Rx4 ECC memory modules, based on Refresh to Active/Refresh 260ns (min.) thirty-six 1G x 4-bit FBGA components per module. Total kit Command Time (tRFCmin) capcity is 48GB. The SPDs are programmed to JEDEC stan- Row Active Time (tRASmin) 34ns (min.) dard latency DDR3-1866 timing of 13-13-13 at 1.5V. Each 240- Maximum Operating Power 6.330 W* (per module) pin DIMM uses gold contact fingers. The electrical and me- UL Rating 94 V - 0 chanical specifications are as follows: o o Operating Temperature 0 C to 85 C o o Storage Temperature -55 C to +100 C FEATURES *Power will vary depending on the SDRAM and JEDEC standard 1.5V (1.425V ~1.575V) Power Supply Register/PLL used. VDDQ = 1.5V (1.425V ~ 1.575V) 933MHz fCK for 1866Mb/sec/pin 8 independent internal bank Programmable CAS Latency: 13, 11, 10, 9, 8, 7, 6 Programmable Additive Latency: 0, CL - 2, or CL - 1 clock 8-bit pre-fetch Burst Length: 8 (Interleave without any limit, sequential with starting address 000 only), 4 with tCCD = 4 which does not allow seamless read or write either on the fly using A12 or MRS Bi-directional Differential Data Strobe Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm 1%) On Die Termination using ODT pin On-DIMM thermal sensor (Grade B) Average Refresh Period 7.8us at lower than TCASE 85C, 3.9us at 85C < TCASE < 95C Asynchronous Reset PCB : Height 1.180 (30.00mm), double sided component Continued >> Document No. VALUERAM1411-001.A00 02/11/14 Page 1MODULE DIMENSIONS Document No. VALUERAM1411-001.A00 Page 2