CORDIC-XM-U1 Lattice

CORDIC IP Core User Guide FPGA-IPUG-02044 Version 1.4 July 2018 CORDIC IP Core User Guide Contents Acronyms in This Document ................................................................................................................................................. 5 1. Introduction .................................................................................................................................................................. 6 2. Quick Facts .................................................................................................................................................................... 7 3. Features ...................................................................................................................................................................... 12 4. Functional Description ................................................................................................................................................ 13 4.1. General Description of the CORDIC Algorithm .................................................................................................. 13 4.2. Block Diagram.................................................................................................................................................... 15 4.2.1. Data Path ...................................................................................................................................................... 15 4.2.1.1. Pre-processor ....................................................................................................................................... 15 4.2.1.2. CORDIC Arithmetic Unit ....................................................................................................................... 15 4.2.1.3. Arctan ROM .......................................................................................................................................... 15 4.2.1.4. Controller ............................................................................................................................................. 15 4.2.1.5. Post-processor...................................................................................................................................... 15 4.2.1.6. Rounding .............................................................................................................................................. 16 4.2.2. CORDIC Functions ......................................................................................................................................... 16 4.2.2.1. Vector Rotation .................................................................................................................................... 16 4.2.2.2. Vector Translation ................................................................................................................................ 17 4.2.2.3. Sin and Cos ........................................................................................................................................... 17 4.2.2.4. Arctan ................................................................................................................................................... 18 4.3. Interface Diagram .............................................................................................................................................. 18 4.4. Configuring the CORDIC IP Core ........................................................................................................................ 19 4.4.1. Basic Options ................................................................................................................................................ 19 4.4.1.1. Architecture Specification .................................................................................................................... 19 4.4.1.2. Iterations Specification ........................................................................................................................ 20 4.4.1.3. Pre-rotation Specification .................................................................................................................... 20 4.4.1.4. Compensation Specification ................................................................................................................. 20 4.4.2. Advanced Options ......................................................................................................................................... 20 4.4.2.1. Round Method Specification ................................................................................................................ 20 4.4.2.2. Input/Output Width Specification ........................................................................................................ 21 4.4.2.3. Data Format Specification .................................................................................................................... 21 4.4.2.4. Phase Format Specification .................................................................................................................. 21 4.4.2.5. Synthesis Options Specification ........................................................................................................... 22 4.5. Timing Specification .......................................................................................................................................... 22 5. Parameter Settings ..................................................................................................................................................... 24 5.1. Basic Options Tab .............................................................................................................................................. 24 5.1.1. Mode ............................................................................................................................................................. 25 5.1.2. Architecture .................................................................................................................................................. 25 5.1.3. Iterations ....................................................................................................................................................... 25 5.1.4. Compensation ............................................................................................................................................... 25 5.1.5. Pre-Rotation .................................................................................................................................................. 25 5.2. Advanced Options Tab ...................................................................................................................................... 25 5.2.1. Data Width .................................................................................................................................................... 25 5.2.2. Rounding ....................................................................................................................................................... 25 5.2.3. Optional Ports ............................................................................................................................................... 25 5.2.3.1. Synchronous Reset ............................................................................................................................... 25 5.2.3.2. Clock Enable ......................................................................................................................................... 26 5.2.4. Synthesis Options .......................................................................................................................................... 26 5.2.4.1. Frequency Constraints (MHz) ............................................................................................................... 26 5.2.4.2. Pipelining and Retiming ....................................................................................................................... 26 6. IP Core Generation ..................................................................................................................................................... 27 6.1. Licensing the IP Core ......................................................................................................................................... 27 6.2. Getting Started .................................................................................................................................................. 27 2009-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02044-1.4