CPRI-E5-UT Lattice

CPRI IP Core User Guide FPGA-IPUG-02029 Version 2.8 July 2017 CPRI IP Core User Guide Contents 1. Introduction .................................................................................................................................................................. 4 1.1. Quick Facts .......................................................................................................................................................... 5 1.2. Features ............................................................................................................................................................... 6 2. Functional Description .................................................................................................................................................. 8 2.1. Block Diagram...................................................................................................................................................... 8 2.2. General Description............................................................................................................................................. 9 2.3. Functional Overview.......................................................................................................................................... 12 2.4. Signal Descriptions ............................................................................................................................................ 13 2.5. Timing Specifications ......................................................................................................................................... 16 2.6. CPRI Overview ................................................................................................................................................... 16 2.7. Interfaces........................................................................................................................................................... 19 2.7.1. User Plane IQ Data Interface ........................................................................................................................ 19 2.7.2. Ethernet Interface ........................................................................................................................................ 21 2.7.3. HDLC Interface .............................................................................................................................................. 23 2.7.4. L1 Inband Protocol Interface ........................................................................................................................ 24 2.7.5. Vendor Specific Information ......................................................................................................................... 24 2.7.6. Start-up Sequence ........................................................................................................................................ 25 3. Parameter Settings ..................................................................................................................................................... 26 3.1. CPRI Configuration Dialog Box .......................................................................................................................... 26 3.1.1. Generation Options ...................................................................................................................................... 28 3.1.2. Eval Configuration ........................................................................................................................................ 28 3.2. Programmable Parameters ............................................................................................................................... 28 4. IP Core Generation ..................................................................................................................................................... 29 4.1. Licensing the IP Core ......................................................................................................................................... 29 4.2. Getting Started .................................................................................................................................................. 29 4.3. IPexpress-Created Files and Top Level Directory Structure .............................................................................. 32 4.4. Instantiating the Core ........................................................................................................................................ 35 4.5. Running Functional Simulation ......................................................................................................................... 36 4.5.1. Using Aldec Active-HDL ................................................................................................................................ 36 4.5.2. Using Mentor Graphics ModelSim ............................................................................................................... 36 4.6. Synthesizing and Implementing the Core in a Top-Level Design ...................................................................... 37 4.7. Hardware Evaluation ......................................................................................................................................... 37 4.7.1. Enabling Hardware Evaluation in Diamond .................................................................................................. 37 4.8. Updating/Regenerating the IP Core .................................................................................................................. 38 4.8.1. Regenerating an IP Core in IPexpress Tool ................................................................................................... 38 4.8.2. Regenerating an IP Core in Clarity Designer Tool ......................................................................................... 38 5. Application Support .................................................................................................................................................... 40 5.1. CPRI IP Top-Level Reference Design .................................................................................................................. 40 5.1.1. Test Bench .................................................................................................................................................... 40 5.1.2. Register Descriptions .................................................................................................................................... 41 References .......................................................................................................................................................................... 46 Technical Support Assistance ............................................................................................................................................. 46 Appendix A. Resource Utilization ....................................................................................................................................... 47 LatticeECP3-FPGAs ........................................................................................................................................................ 47 ECP5 FPGAs (for 3G Version) .......................................................................................................................................... 47 ECP5 FPGAs (for 5G Version) .......................................................................................................................................... 47 Revision History .................................................................................................................................................................. 48 2006-2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 FPGA-IPUG-02029-2.8