DDR2CTWB-M2-U Lattice

DDR & DDR2 SDRAM Controller for MachXO2 PLD Family IP Cores User Guide (Piplelined Versions) March 2015 IPUG93 1.2Table of Contents Chapter 1. Introduction .......................................................................................................................... 5 Quick Facts ........................................................................................................................................................... 5 Features ................................................................................................................................................................ 6 Chapter 2. Functional Description ........................................................................................................ 7 Command Decode Logic.............................................................................................................................. 7 Configuration Interface................................................................................................................................. 7 sysCLOCK PLL............................................................................................................................................ 8 Data Path Logic............................................................................................................................................ 8 Initialization State Machine .......................................................................................................................... 8 Command Application Logic ........................................................................................................................ 8 DDR I/O Modules......................................................................................................................................... 8 Signal Descriptions ............................................................................................................................................... 8 Using the Local User Interface.............................................................................................................................. 9 Initialization and Auto-Refresh Control....................................................................................................... 10 Command and Address ............................................................................................................................. 11 Data Write .................................................................................................................................................. 12 Data Read.................................................................................................................................................. 13 Read/Write with Auto Precharge................................................................................................................ 13 Local-to-Memory Address Mapping ........................................................................................................... 13 Mode Register Programming ..................................................................................................................... 14 Memory Interface ................................................................................................................................................ 17 Chapter 3. Parameter Settings ............................................................................................................ 18 Mode Tab............................................................................................................................................................ 19 Type Tab............................................................................................................................................................. 20 Select Memory ........................................................................................................................................... 20 Clock .......................................................................................................................................................... 20 Memory Data Bus Size .............................................................................................................................. 20 Configuration.............................................................................................................................................. 20 Data rdy to Write Data Delay .................................................................................................................... 20 Clock Width................................................................................................................................................ 20 CKE Width.................................................................................................................................................. 21 Fixed Memory Timing................................................................................................................................. 21 Setting Tab.......................................................................................................................................................... 21 Row Size.................................................................................................................................................... 21 Column Size............................................................................................................................................... 21 Bank Size................................................................................................................................................... 22 Chip Select Width....................................................................................................................................... 22 User Slot Size ............................................................................................................................................ 22 EMR Prog During Init ................................................................................................................................. 22 Auto Refresh Burst Count .......................................................................................................................... 22 External Auto Refresh Port ........................................................................................................................ 22 Mode Register Initial Setting ...................................................................................................................... 22 Timing Tab .......................................................................................................................................................... 22 Synthesis & Simulation Tools Option Tab........................................................................................................... 24 Info Tab............................................................................................................................................................... 24 Chapter 4. IP Core Generation............................................................................................................. 25 Licensing the IP Core.......................................................................................................................................... 25 Getting Started.................................................................................................................................................... 25 IPexpress-Created Files and Top Level Directory Structure............................................................................... 27 Generated Files................................................................................................................................................... 27 IPUG93 1.2, March 2015 2 DDR & DDR2 for MachXO2 PLD Family Users Guide