DDR3-P-E3-UT1 Lattice

Double Data Rate (DDR3) SDRAM Controller IP Core Users Guide March 2012 IPUG80 01.5Table of Contents Chapter 1. Introduction .......................................................................................................................... 5 Quick Facts ........................................................................................................................................................... 5 Features ................................................................................................................................................................ 5 Chapter 2. Functional Description ........................................................................................................ 7 Overview ............................................................................................................................................................... 7 DDR3 MC Module ................................................................................................................................................. 8 Command Decode Logic.............................................................................................................................. 8 Command Application Logic ........................................................................................................................ 8 On-Die Termination...................................................................................................................................... 8 DDR3 PHY Module ............................................................................................................................................... 8 Initialization Module............................................................................................................................................... 9 Write Leveling .............................................................................................................................................. 9 Data Path Logic............................................................................................................................................ 9 Signal Descriptions ............................................................................................................................................... 9 Using Local User Interface.................................................................................................................................. 11 Initialization Control.................................................................................................................................... 12 Command and Address ............................................................................................................................. 12 User Commands ........................................................................................................................................ 14 WRITE........................................................................................................................................................ 14 WRITEA ..................................................................................................................................................... 15 READ ......................................................................................................................................................... 15 READA....................................................................................................................................................... 16 REFRESH Support .................................................................................................................................... 16 Local-to-Memory Address Mapping .................................................................................................................... 17 Mode Register Programming .............................................................................................................................. 17 Chapter 3. Parameter Settings ............................................................................................................ 19 Type Tab............................................................................................................................................................. 21 Select Memory ........................................................................................................................................... 22 Clock .......................................................................................................................................................... 22 Memory Type ............................................................................................................................................. 22 Memory Data Bus Size .............................................................................................................................. 22 Configuration.............................................................................................................................................. 22 DIMM Type or Chip Select Width............................................................................................................... 22 Address Mirror............................................................................................................................................ 22 Clock Width................................................................................................................................................ 22 CKE Width.................................................................................................................................................. 22 2T MODE ................................................................................................................................................... 23 Data rdy to Write Data Delay .................................................................................................................... 23 Write Leveling ............................................................................................................................................ 23 Controller Reset to Memory ....................................................................................................................... 23 Setting Tab.......................................................................................................................................................... 23 Row Size.................................................................................................................................................... 23 Column Size............................................................................................................................................... 24 Auto Refresh Burst Count .......................................................................................................................... 24 External Auto Refresh Port ........................................................................................................................ 24 Burst Length............................................................................................................................................... 24 CAS Latency .............................................................................................................................................. 24 Burst Type.................................................................................................................................................. 24 Write Recovery........................................................................................................................................... 24 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG80 01.5, March 2012 2 DDR3 SDRAM Controller IP Core Users Guide