DDRCT-AHB-O4-N1 Lattice

TM ispLever CORECORE Double Data Rate (DDR) SDRAM Controller (Pipelined Version) Users Guide June 2004 ipug12 03 Double Data Rate (DDR) SDRAM Controller Lattice Semiconductor (Pipelined Version) Users Guide Introduction DDR (Double Data Rate) SDRAM was introduced as a replacement for SDRAM memory running at bus speeds over 75MHz. DDR SDRAM is similar in function to regular SDRAM but doubles the bandwidth of the memory by transferring data twice per cycle (on both edges of the clock signal), implementing burst mode data transfer. The DDR SDRAM Controller is a parameterized core. This allows the user to modify the data widths, burst transfer rates, and CAS latency settings of the design. In addition, the DDR core supports intelligent bank management. By maintaining a database of all banks activated and the rows activated in each bank, the DDR SDRAM Controller decides if an active or pre-charge command is needed. This effectively reduces the latency of read/write com- mands issued to the DDR SDRAM. Since the DDR SDRAM Controller takes care of activating/pre-charging the banks, the user can simply issue sim- ple read/write commands without regard to the bank/charge status. Features Performance of Greater than 100MHz (200 DDR) Interfaces to JEDEC Standard DDR SDRAMs Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits Supports up to 8 External Memory Banks Programmable Burst Lengths of 2, 4, or 8 Programmable CAS Latency of 1.5, 2.0, 2.5 or 3.0 Byte-level Writing Supported Increased Throughput Using Command Pipelining and Bank Management Supports Power-down and Self Refresh Modes Automatic Initialization Automatic Refresh During Normal and Power-down Modes Timing and Settings Parameters Implemented as Programmable Registers Bus Interfaces to PCI Target, PowerPC and AMBA (AHB) Buses Available Complete Synchronous Implementation 2