NEXT GENERATION DESIGN SOFTWARE Lattice Diamond Leading-edge design and implementation tools optimized for Lattice FPGA architectures. Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost-sensi- tive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numer - ous other enhancements. This combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. Diamond software is available as a download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either a free license or a subscription license. Diamond Software Free License A free license can be requested from the Lattice website. This license provides immediate access to many popular Lattice devices such as MachXO2, MachXO, LatticeXP2 and Key Features and Benefits LatticeECP2 at no cost. It also includes Synopsys Synplify Pro for Lattice synthesis and Aldec Active-HDL Lattice Design Exploration Features Edition II mixed language simulator.* Explore design alter natives with Implementations & Strategies Diamond Software Subscription License Run Manager for accelerating exploration and utilizing A subscription license can be purchased which adds sup- multi-core processors port for all Lattice FPGAs including the latest MachXO2 and Integrated HDL code checking LatticeECP3 devices. It includes Synopsys Synplify Pro Lattice Synthesis Engine (LSE) for additional synthesis for Lattice synthesis and Aldec Active-HDL Lattice Edition II exploration options. mixed language simulator*. Ease-of-Use Features Advanced next generation user interface Centralized reports and messaging Extensive cross-probing support Manage multiple constraint, preference, debug, timing analyzer, and power calculator files within file list view ECO Editor for specific physical netlist-level changes Programmer for improved programming support SUPERIOR DESIGN EXPLORATION Improved Design Flow New Timing Analyzer view allows updated timing EASE OF USE analysis, including clock jitter analysis, without re- implementing the design IMPROVED DESIGN FLOW Simulation Wizard for exporting designs Extensive Tcl scripting dictionaries Additional Software Included with Diamond LatticeMico system integration for embedded microprocessor applications EPIC full-featured physical netlist-level editor *Aldec Active-HDL Lattice Edition II simulator is only available for Windows. Floating licenses require the additional ALDEC-USBKEY product. www.latticesemi.com/latticediamondDiamond Key New Features HDL cODE cHEcKING SYNTHESIS OPTIONS Design Exploration Save time by analyzing your design prior In addition to Synplify Pro for all devic- PROEj cTS / IMPLEMENTATIONS / to synthesis with Diamond s integrated es, for MachXO2 and MachXO de- STRATEGIES HDL code checking capability. Click vices the new Lattice Synthesis Engine Diamond allows more robust projects Generate Hierarchy and HDL Diagram, (LSE) is also available for exploring how and offers new capabilities for im- Hierarchy, Module, and Dictionary views to achieve the best results. LSE supports proved design exploration. Key features become available to help in analyzing both Verilog and VHDL languages and include: your design. Additionally, a number of uses the Synopsys Design Compiler Con- Mixing of Verilog, VHDL, EDIF, BKM (Best Known Methods) rule checks straints format for constraints. and schematic sources can be run against your design. Implementations allow multiple versions of a design within a single project for easy design exploration Strategies allow implementation recipes to be applied to any implementation within a project or shared between projects Manage and choose files for con- straints, timing analysis, power calculation, and hardware debug Use Run Manager view for paral- lel processing of multiple imple- mentations to explore design alternatives for the best results Diamond Environment for Design Exploration Ease of Use KEY GUI ELEMENTS SPEED cOMMON FUNcTIONS WITH EcO EDITOR & PROGRAMMER GUI FOR A NEW GENERATION OF Common menu and button TOOLS locations for all views ECO Editor provides quick access to commonly used physical netlist The Diamond user interface combines Three user interface sections for editing functions without using the leading edge features and customiza- tools, projects, and output EPIC full editor tion while offering improved ease of Start Page Open projects, import Programmer allows fast program- use. All tools open in Views integrated ispLEVER projects, online help, ming of FPGAs into a common user interface. Once the software updates operation for a single tool is learned, this Report View Centralized location knowledge can be applied to other tools. for all reports from implementation tools ScRIPTING WITH Tcl Improved Design Flow Tcl command dictionar- FAST, EASY TIMING ANALYSIS ies for projects, netlists, Timing Analysis view offers an easy-to- HDL code checking, use graphical environment for navigating power calculation, and timing information. hardware debug. Click on a constraint and see the In addition to the Tcl timing paths, detailed paths, and console in the Diamond path schematic views instantly environment, a separate Tcl console application Easy visual cues provide instant allows running scripts design feedback. independently. Rapidly updated analysis when Diamond Timing Analysis View timing constraints are changed EASY EXPORT TO SIMULATORS Add clock jitter analysis to your design to Aldec or ModelSim The new Simulation Wizard guides you improve the robustness of your simulators in the format you choose. through all the necessary steps to get design