DMA-MC-E2-N3 Lattice

TM ispLever CORECORE Multi-Channel DMA Controller Users Guide February 2006 ipug11 04.0 Lattice Semiconductor Multi-Channel DMA Controller Users Guide Introduction The Multi-Channel Direct Memory Access (MCDMA) Controller is designed to improve microprocessor system per- formance by allowing external devices to transfer information directly from the system memory and vice versa. Memory-to-memory transfer capability is also supported. The MCDMA Controller core supports two modes of operation: 8237 and non-8237 modes. When the 8237 mode is selected, the core is functionally compatible with the Intel 8237A DMA Controller device with a few variations. These variations are listed in the Compatibility Differences with the 8237 Intel Device section of this document. The 8237 and non-8237 modes are detailed later in this document to provide a clearer description of each mode. Differences Between 8237 Mode and Non-8237 Mode MCDMA While the 8237 and non-8237 modes share some commonality, they also have differences. Table 1 shows the dif- ferences between the two modes. Table 1. Feature Differences Between the 8237 and Non-8237 Modes Feature 8237 Mode Non-8237 Mode Multiple independent channels 4 1-16 Parameterized address bus Fixed 16 bits 16, 24 or 32 bits Parameterized data bus Fixed 8 bits 8, 16, 32 or 64 bits Parameterized word count register Fixed 16 bits 8, 16, 24 or 32 bits Auto-initialization Supported Supported Compressed timing Supported Not supported Cascade mode Not supported Not supported DMA transfer conguration for each channel Not supported Supported Priority request mode Rotating/xed priority mode Fixed priority mode DMA request active state High/low High Software reset Supported Not supported Compatibility Differences with the 8237 Intel Device When the MCDMA core is congured for the 8237 mode, it differs from the Intel 8237A core in the following ways: The bi-directional ports are split into separate input and output ports. MCDMA does not support the cascade mode of operation. The latch that holds the upper byte of the address is internal and the address strobe signal ADSTB is not gener- ated. The slaves write cycle in the MCDMA core is synchronous. Features Selectable 8237 mode Congurable up to 16 independent DMA channels for non-8237 mode Congurable data width of 8-, 16-, 32- or 64-bits for non-8237 mode Congurable address width of 16-, 24- or 32-bits for non-8237 mode Congurable Word Count register width for non-8237 mode Independent auto-initialization of all channels Memory-to-memory transfers on single, block, and demand transfer mode Memory block initialization 2