FIR-COMP-P2-UT3 Lattice

FIR Filter IP Core Users Guide April 2014 IPUG79 01.4Table of Contents Chapter 1. Introduction .......................................................................................................................... 4 Quick Facts ........................................................................................................................................................... 4 Features ................................................................................................................................................................ 7 Chapter 2. Functional Description ........................................................................................................ 8 Interface Diagram.................................................................................................................................................. 8 FIR Filter Architecture ........................................................................................................................................... 8 Direct-form Implementation.......................................................................................................................... 8 Symmetric Implementation........................................................................................................................... 9 Polyphase Interpolation FIR Filter................................................................................................................ 9 Polyphase Decimation FIR Filter................................................................................................................ 10 Multi-channel FIR Filters ............................................................................................................................ 10 Implementation Details........................................................................................................................................ 10 Configuring the FIR Filter IP Core....................................................................................................................... 11 Architecture Options................................................................................................................................... 11 I/O Specification Options............................................................................................................................ 13 Implementation Options ............................................................................................................................. 13 Signal Descriptions ............................................................................................................................................. 13 Interfacing with the FIR Filter IP core.................................................................................................................. 14 Data interface............................................................................................................................................. 14 Multiple Channels....................................................................................................................................... 14 Variable Interpolation/ Decimation Factor.................................................................................................. 15 Reloadable Coefficients ............................................................................................................................. 15 Timing Specifications .......................................................................................................................................... 16 Timing Specifications Applicable to All Devices......................................................................................... 16 Timing Specifications Applicable to LatticeXP2 and Certain LatticeECP3 Implementations ..................... 17 Timing Specifications Applicable to Certain LatticeECP3 Implementations............................................... 18 Timing specifications Applicable to ECP5 Implementations ...................................................................... 19 Chapter 3. Parameter Settings ............................................................................................................ 21 Architecture Tab.................................................................................................................................................. 23 Select ECP5 High Speed sysDSP Mode ................................................................................................... 23 Multi-channel.............................................................................................................................................. 23 Single-channel ........................................................................................................................................... 23 Number of Channels .................................................................................................................................. 23 Number of Taps ......................................................................................................................................... 23 Filter Type .................................................................................................................................................. 23 Interpolation Factor .................................................................................................................................... 23 Variable Interpolation Factor...................................................................................................................... 23 Decimation Factor...................................................................................................................................... 24 Variable Decimation Factor........................................................................................................................ 24 Reloadable Coefficients ............................................................................................................................. 24 Reorder Coefficients Inside........................................................................................................................ 24 Coefficients set........................................................................................................................................... 24 Symmetric Coefficients .............................................................................................................................. 24 Negative Symmetry.................................................................................................................................... 24 Half Band ................................................................................................................................................... 24 Coefficient Radix........................................................................................................................................ 24 Coefficients File.......................................................................................................................................... 24 Multiplier Multiplexing Factor...................................................................................................................... 25 Number of sysDSP Blocks in a Row.......................................................................................................... 25 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. IPUG79 01.4, April 2014 2 FIR Filter IP Core Users Guide