GAL 16LV8C/D Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line Ordering Part Number Product Status Reference PCN
GAL16LV8C-7LJ
PCN#06-07
GAL16LV8C-7LJN
GAL16LV8C-10LJ
GAL16LV8C
GAL16LV8C-10LJN
GAL16LV8C-15LJ
Discontinued
GAL16LV8C-15LJN
PCN#09-10
GAL16LV8D-3LJ
GAL16LV8D-3LJN
GAL16LV8D
GAL16LV8D-5LJ
GAL16LV8D-5LJN
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: GAL16LV8
2
Low Voltage E CMOS PLD
Generic Array Logic
Features Functional Block Diagram
2
HIGH PERFORMANCE E CMOS TECHNOLOGY
I/CLK
3.5 ns Maximum Propagation Delay CLK
Fmax = 250 MHz
2.5 ns Maximum from Clock Input to Data Output
I/O/Q
8
OLMC
UltraMOS Advanced CMOS Technology
I
3.3V LOW VOLTAGE 16V8 ARCHITECTURE
JEDEC-Compatible 3.3V Interface Standard
8 OLMC I/O/Q
5V Compatible Inputs
I/O Interfaces with Standard 5V TTL Devices I
(GAL16LV8C)
OLMC I/O/Q
8
ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
I
2
E CELL TECHNOLOGY
Reconfigurable Logic
OLMC I/O/Q
8
Reprogrammable Cells
100% Tested/100% Yields
I
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
8 OLMC I/O/Q
EIGHT OUTPUT LOGIC MACROCELLS
I
Maximum Flexibility for Complex Logic Designs
Programmable Output Polarity
OLMC I/O/Q
8
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
I
100% Functional Testability
OLMC I/O/Q
8
APPLICATIONS INCLUDE:
Glue Logic for 3.3V Systems
I
DMA Control
State Machine Control
OLMC I/O/Q
8
High Speed Graphics Processing
I
Standard Logic Speed Upgrade
OE
I/OE
ELECTRONIC SIGNATURE FOR IDENTIFICATION
LEAD-FREE PACKAGE OPTIONS
Description Pin Configuration
The GAL16LV8D, at 3.5 ns maximum propagation delay time, PLCC
provides the highest speed performance available in the PLD
market. The GAL16LV8C can interface with both 3.3V and 5V
I I I/CLK Vcc I/O/Q
signal levels. The GAL16LV8 is manufactured using Lattice
2
2 20
Semiconductor's advanced 3.3V E CMOS process, which com-
2
18
bines CMOS with Electrically Erasable (E ) floating gate technology. 4 I/O/Q
I
High speed erase times (<100ms) allow the devices to be repro-
grammed quickly and efficiently.
I/O/Q
I
The 3.3V GAL16LV8 uses the same industry standard 16V8 archi- GAL16LV8
6 16 I/O/Q
I
tecture as its 5V counterpart and supports all architectural features
Top View
such as combinatorial or registered macrocell operations.
I/O/Q
I
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lattice
14 I/O/Q
I 8
9 11 13
Semiconductor delivers 100% field programmability and function-
ality of all GAL products. In addition, 100 erase/write cycles and
I GND I/OE I/O/Q I/O/Q
data retention in excess of 20 years are specified.
Copyright 2004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2004
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556;