GAL18V10B-10LJ Lattice

GAL 18V10 Device Datasheet September 2010 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL18V10B-7LJ PCN#06-07 GAL18V10B-7LP GAL18V10B-10LJ GAL18V10B-10LP GAL18V10 Discontinued GAL18V10B-15LJ PCN#13-10 GAL18V10B-15LP GAL18V10B-20LJ GAL18V10B-20LP 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: GAL18V10 2 High Performance E CMOS PLD Generic Array Logic Features Functional Block Diagram 2 HIGH PERFORMANCE E CMOS TECHNOLOGY 7.5 ns Maximum Propagation Delay RESET Fmax = 111 MHz I/CLK 5.5 ns Maximum from Clock Input to Data Output 8 TTL Compatible 16 mA Outputs OLMC I/O/Q UltraMOS Advanced CMOS Technology I 8 LOW POWER CMOS OLMC I/O/Q 75 mA Typical Icc ACTIVE PULL-UPS ON ALL PINS 8 OLMC I/O/Q 2 E CELL TECHNOLOGY I Reconfigurable Logic 8 Reprogrammable Cells OLMC I/O/Q 100% Tested/100% Yields High Speed Electrical Erasure (<100ms) I 10 20 Year Data Retention OLMC I/O/Q TEN OUTPUT LOGIC MACROCELLS Uses Standard 22V10 Macrocell Architecture 10 OLMC I/O/Q I Maximum Flexibility for Complex Logic Designs PRELOAD AND POWER-ON RESET OF REGISTERS 8 100% Functional Testability OLMC I/O/Q APPLICATIONS INCLUDE: I 8 DMA Control OLMC I/O/Q State Machine Control High Speed Graphics Processing 8 Standard Logic Speed Upgrade I OLMC I/O/Q ELECTRONIC SIGNATURE FOR IDENTIFICATION 8 OLMC I/O/Q Description I PRESET The GAL18V10, at 7.5 ns maximum propagation delay time, com- bines a high performance CMOS process with Electrically Eras- 2 able (E ) floating gate technology to provide a very flexible 20-pin Pin Configuration PLD. CMOS circuitry allows the GAL18V10 to consume much less 2 power when compared to its bipolar counterparts. The E technol- DIP ogy offers high speed (<100ms) erase times, providing the ability PLCC to reprogram or reconfigure the device quickly and efficiently. 1 20 Vcc I/CLK By building on the popular 22V10 architecture, the GAL18V10 I/O/Q I I I I/CLK Vcc I/O/Q eliminates the learning curve usually associated with using a new 2 20 I/O/Q I device architecture. The generic architecture provides maximum GAL 18 I 4 I/O/Q design flexibility by allowing the Output Logic Macrocell (OLMC) I/O/Q I 18V10 I/O/Q I to be configured by the user. The GAL18V10 OLMC is fully com- I/O/Q 5 I patible with the OLMC in standard bipolar and CMOS 22V10 de- GAL18V10 I 6 16 I/O/Q vices. 15 I/O/Q I Top View I/O/Q I Unique test circuitry and reprogrammable cells allow complete AC, I/O/Q I I 8 14 I/O/Q DC, and functional testing during manufacture. As a result, Lattice 9 11 13 I I/O/Q Semiconductor delivers 100% field programmability and function- I/O/Q GND I/O/Q I/O/Q I/O/Q ality of all GAL products. In addition, 100 erase/write cycles and I/O/Q I/O/Q data retention in excess of 20 years are specified. GND 10 11 I/O/Q Copyright 2003 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. November 2003 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556;