GAL20RA10B-15LPN Lattice

GAL 20RA10 Device Datasheet June 2010 All Devices Discontinued! Product Change Notification (PCN) #09-10 has been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL20RA10B-10LP GAL20RA10B-15LP GAL20RA10B-20LP GAL20RA10B-30LP GAL20RA10B-20LPI Discontinued PCN#09-10 GAL20RA10B-7LJ GAL20RA10 GAL20RA10B-10LJ GAL20RA10B-15LJ GAL20RA10B-20LJ GAL20RA10B-30LJ GAL20RA10B-20LJI 5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347 Internet: GAL20RA10 2 High-Speed Asynchronous E CMOS PLD Generic Array Logic Features Functional Block Diagram 2 HIGH PERFORMANCE E CMOS TECHNOLOGY PL 7.5 ns Maximum Propagation Delay Fmax = 83.3 MHz 9 ns Maximum from Clock Input to Data Output 8 OLMC I I/O/Q TTL Compatible 8 mA Outputs UltraMOS Advanced CMOS Technology 8 50% to 75% REDUCTION IN POWER FROM BIPOLAR I OLMC I/O/Q 75mA Typical Icc 8 ACTIVE PULL-UPS ON ALL PINS OLMC I I/O/Q 2 E CELL TECHNOLOGY Reconfigurable Logic 8 Reprogrammable Cells OLMC I I/O/Q 100% Tested/100% Yields High Speed Electrical Erasure (<100 ms) 8 20 Year Data Retention OLMC I I/O/Q TEN OUTPUT LOGIC MACROCELLS 8 Independent Programmable Clocks OLMC I I/O/Q Independent Asynchronous Reset and Preset Registered or Combinatorial with Polarity 8 Full Function and Parametric Compatibility with OLMC I I/O/Q PAL20RA10 8 PRELOAD AND POWER-ON RESET OF ALL REGISTERS OLMC I I/O/Q 100% Functional Testability APPLICATIONS INCLUDE: 8 OLMC State Machine Control I I/O/Q Standard Logic Consolidation Multiple Clock Logic Designs 8 OLMC I I/O/Q ELECTRONIC SIGNATURE FOR IDENTIFICATION Description OE The GAL20RA10 combines a high performance CMOS process Pin Configuration 2 with electrically erasable (E ) floating gate technology to provide the highest speed performance available in the PLD market. Lattice DIP 2 Semiconductors E CMOS circuitry achieves power levels as low 1 24 Vcc PLCC PL as 75mA typical I which represents a substantial savings in power CC 2 I/O/Q when compared to bipolar counterparts. E technology offers high I speed (<100ms) erase times providing the ability to reprogram, I/O/Q I reconfigure or test the devices quickly and efficiently. I/O/Q I GAL 4 228 26 I 5 25 I/O/Q I/O/Q I The generic architecture provides maximum design flexibility by 20RA10 I I/O/Q 6 allowing the Output Logic Macrocell (OLMC) to be configured by I I/O/Q I 7 23 I/O/Q the user. The GAL20RA10 is a direct parametric compatible CMOS 18 I/O/Q I GAL20RA10 NC NC replacement for the PAL20RA10 device. I I/O/Q I 9 Top View 21 I/O/Q Unique test circuitry and reprogrammable cells allow complete AC, I I I/O/Q I/O/Q DC, and functional testing during manufacturing. Therefore, Lattice I 11 19 I/O/Q I I/O/Q 12 14 16 18 Semiconductor delivers 100% field programmability and function- I I/O/Q ality of all GAL products. In addition, 100 erase/write cycles and GND 13 OE 12 data retention in excess of 20 years are specified. Copyright 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. July 1997 Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556;