GAL 22LV10 Device Datasheet
June 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line Ordering Part Number Product Status Reference PCN
GAL22LV10C-7LJ
PCN#06-07
GAL22LV10C-7LJN
GAL22LV10C-10LJ
GAL22LV10C Discontinued
GAL22LV10C-10LJN
PCN#09-10
GAL22LV10C-15LJ
GAL22LV10C-15LJN
GAL22LV10D-4LJ
GAL22LV10D-4LJN
GAL22LV10D Discontinued PCN#09-10
GAL22LV10D-5LJ
GAL22LV10D-5LJN
5555 N.E. Moore Ct. z Hillsboro, Oregon 97124-6421 z Phone (503) 268-8000 z FAX (503) 268-8347
Internet: New 5V
Tolerant
Inputs on
22LV10D
GAL22LV10
2
Low Voltage E CMOS PLD
Generic Array Logic
Features Functional Block Diagram
2
HIGH PERFORMANCE E CMOS TECHNOLOGY
RESET
4 ns Maximum Propagation Delay
I/CLK
Fmax = 250 MHz
8
3 ns Maximum from Clock Input to Data Output
OLMC
I/O/Q
UltraMOS Advanced CMOS Technology
I
3.3V LOW VOLTAGE 22V10 ARCHITECTURE
10
OLMC
I/O/Q
JEDEC-Compatible 3.3V Interface Standard
I
5V Compatible Inputs
I/O Interfaces with Standard 5V TTL Devices
12
OLMC
(GAL22LV10C) I/O/Q
I
ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
14
2
OLMC
E CELL TECHNOLOGY I/O/Q
I
Reconfigurable Logic
Reprogrammable Cells
16
I OLMC
100% Tested/100% Yields I/O/Q
High Speed Electrical Erasure (<100ms)
20 Year Data Retention
16
I
OLMC I/O/Q
TEN OUTPUT LOGIC MACROCELLS
Maximum Flexibility for Complex Logic Designs
14
Programmable Output Polarity
I
OLMC
I/O/Q
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
100% Functional Testability
I 12
OLMC
I/O/Q
APPLICATIONS INCLUDE:
Glue Logic for 3.3V Systems
I
10
DMA Control
OLMC
I/O/Q
State Machine Control
High Speed Graphics Processing
I
Standard Logic Speed Upgrade 8
OLMC
I/O/Q
ELECTRONIC SIGNATURE FOR IDENTIFICATION
I
PRESET
LEAD-FREE PACKAGE OPTIONS
Description Pin Configuration
PLCC
The GAL22LV10D, at 4 ns maximum propagation delay time, pro-
vides the highest speed performance available in the PLD market.
The GAL22LV10C can interface with both 3.3V and 5V signal levels.
The GAL22LV10 is manufactured using Lattice Semiconductor's
2
422286
advanced 3.3V E CMOS process, which combines CMOS with
2
I 5 25 I/O/Q
Electrically Erasable (E ) floating gate technology. High speed erase
times (<100ms) allow the devices to be reprogrammed quickly and
I I/O/Q
efficiently.
I 7 23
I/O/Q
The generic architecture provides maximum design flexibility by GAL22LV10
NC
NC
allowing the Output Logic Macrocell (OLMC) to be configured by
Top View
the user.
I 9 21
I/O/Q
Unique test circuitry and reprogrammable cells allow complete AC,
I
I/O/Q
DC, and functional testing during manufacture. As a result, Lattice
I
11 19
I/O/Q
Semiconductor delivers 100% field programmability and function-
12 14 16 18
ality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright 2008 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2008
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556;