GAL 26CV12 Device Datasheet September 2010 All Devices Discontinued Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number Product Status Reference PCN GAL26CV12B-10LP GAL26CV12B-15LP GAL26CV12B-20LP PCN 06-07 GAL26CV12B-15LPI GAL26CV12B-20LPI GAL26CV12B GAL26CV12B-10LJ GAL26CV12B-15LJ Discontinued GAL26CV12B-20LJ PCN 13-10 GAL26CV12B-15LJI GAL26CV12B-20LJI GAL26CV12C-7LP PCN 06-07 GAL26CV12C-10LPI GAL26CV12C GAL26CV12C-7LJ PCN 13-10 GAL26CV12C-10LJI 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347 Internet: GAL26CV12 2 High Performance E CMOS PLD Generic Array Logic Features Functional Block Diagram 2 HIGH PERFORMANCE E CMOS TECHNOLOGY 7.5 ns Maximum Propagation Delay I/CLK INPUT Fmax = 142.8 MHz RESET 8 4.5ns Maximum from Clock Input to Data Output I/O/Q OLMC I TTL Compatible 16 mA Outputs UltraMOS Advanced CMOS Technology 8 I/O/Q OLMC I ACTIVE PULL-UPS ON ALL PINS 8 I/O/Q LOW POWER CMOS OLMC I 90 mA Typical Icc 8 I/O/Q 2 OLMC E CELL TECHNOLOGY I Reconfigurable Logic 10 I/O/Q Reprogrammable Cells OLMC I 100% Tested/100% Yields 12 High Speed Electrical Erasure (<100ms) I/O/Q OLMC I 20 Year Data Retention 12 I/O/Q TWELVE OUTPUT LOGIC MACROCELLS OLMC I Uses Standard 22V10 Macrocells 10 Maximum Flexibility for Complex Logic Designs I/O/Q OLMC I PRELOAD AND POWER-ON RESET OF REGISTERS 8 I/O/Q 100% Functional Testability OLMC I APPLICATIONS INCLUDE: 8 I/O/Q OLMC DMA Control I State Machine Control 8 I/O/Q High Speed Graphics Processing OLMC I Standard Logic Speed Upgrade 8 I/O/Q OLMC ELECTRONIC SIGNATURE FOR IDENTIFICATION I PRESET Description The GAL26CV12, at 7.5 ns maximum propagation delay time, Pin Configuration combines a high performance CMOS process with Electrically 2 Erasable (E ) floating gate technology to provide the highest DIP 2 performance 28-pin PLD available on the market. E technology offers high speed (<100ms) erase times, providing the ability to 128 I I/CLK reprogram or reconfigure the device quickly and efficiently. PLCC I/O/Q I Expanding upon the industry standard 22V10 architecture, the I I/O/Q GAL26CV12 eliminates the learning curve typically associated with I I/O/Q using a new device architecture. The generic architecture provides GAL 422 286 I I/O/Q maximum design flexibility by allowing the Output Logic Macrocell 26CV12 5 25 I I/O/Q I I/O/Q (OLMC) to be configured by the user. The GAL26CV12 OLMC is I I/O/Q Vcc 7 I/O/Q fully compatible with the OLMC in standard bipolar and CMOS 7 VCC 23 I/O/Q 22V10 devices. GAL26CV12 I 21 GND I I/O/Q 9 I I/O/Q I 21 Top View GND Unique test circuitry and reprogrammable cells allow complete AC, I I/O/Q I I/O/Q DC, and functional testing during manufacture. As a result, Lattice 11 I 19 I/O/Q I I/O/Q Semiconductor delivers100% field programmability and functionality 12 14 16 18 of all GAL products. In addition, 100 erase/write cycles and data I/O/Q I retention in excess of 20 years are specified. I I/O/Q I 14 15 I/O/Q Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. June 2000 Tel. (503) 268-8000 1-800-LATTICE FAX (503) 268-8556