GAL 26V12 Device Datasheet
September 2010
All Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue all devices in this
data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line Ordering Part Number Product Status Reference PCN
GAL26V12C-10LP
GAL26V12C-15LP
GAL26V12C-20LP
PCN#06-07
GAL26V12C-10LPI
GAL26V12C-15LPI
GAL26V12C-20LPI
GAL26V12 GAL26V12C-7LJ Discontinued
GAL26V12C-10LJ
GAL26V12C-15LJ
GAL26V12C-20LJ PCN#13-10
GAL26V12C-10LJI
GAL26V12C-15LJI
GAL26V12C-20LJI
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: Select devices have been discontinued.
See Ordering Information section for product status.
GAL26V12
2
High Performance E CMOS PLD
TM
Generic Array Logic
FEATURES FUNCTIONAL BLOCK DIAGRAM
2
HIGH PERFORMANCE E CMOS TECHNOLOGY
7.5 ns Maximum Propagation Delay
I/CLK 1 INPUT
Fmax = 142.8 MHz
PRESET
4.5 ns Maximum from Clock Input to Data Output
8
I/O/Q
TTL Compatible 16 mA Outputs OLMC 0
INPUT
UltraMOS Advanced CMOS Technology
8
I/O/Q
OLMC 1
LOW POWER CMOS INPUT
90 mA Typical Icc
10
I/O/Q
OLMC 2
2
E CELL TECHNOLOGY INPUT/CLK 2
Reconfigurable Logic
12
I/O/Q
OLMC 3
Reprogrammable Cells
INPUT
100% Tested/Guaranteed 100% Yields
14
I/O/Q
High Speed Electrical Erasure (<100ms)
OLMC 4
INPUT
20 Year Data Retention
16
I/O/Q
TWELVE OUTPUT LOGIC MACROCELLS
OLMC 5
INPUT
Maximum Flexibility for Complex Logic Designs
16
I/O/Q
PRELOAD AND POWER-ON RESET OF REGISTERS OLMC 6
INPUT
100% Functional Testability
14
I/O/Q
OLMC 7
INPUT
APPLICATIONS INCLUDE:
DMA Control 12
I/O/Q
State Machine Control OLMC 8
INPUT
High Speed Graphics Processing
10
I/O/Q
Standard Logic Speed Upgrade
OLMC 9
INPUT
ELECTRONIC SIGNATURE FOR IDENTIFICATION
8
I/O/Q
OLMC 10
INPUT
DESCRIPTION
8
I/O/Q
OLMC 11
INPUT
The GAL26V12, at 7.5ns maximum propagation delay time, com-
RESET
bines a high performance CMOS process with Electrically Eras-
2
able (E ) floating gate technology to provide the highest perform-
2
ance available of any 26V12 device on the market. E technol-
PACKAGE DIAGRAMS
ogy offers high speed (<100ms) erase times, providing the ability
to reprogram or reconfigure the device quickly and efficiently.
DIP
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
128 I
I/CLK1
the user. The GAL26V12 is fully function/fuse map/parametric PLCC
I/O/Q
I
compatible with other 26V12 devices.
I I/O/Q
Unique test circuitry and reprogrammable cells allow complete
I/CLK2
I/O/Q
AC, DC, and functional testing during manufacture. As a result,
GAL
I
I/O/Q
422 286
LATTICE is able to guarantee 100% field programmability and
26V12
I I/O/Q
5 25
I
I/O/Q
products. LATTICE also guarantees 100
functionality of all GAL
Vcc 7
I/O/Q
I
I/O/Q
erase/rewrite cycles.
7
VCC I 21 GND
23
GAL26V12 I/O/Q
I I I/O/Q
I/O/Q
Top View
9
I
21 I
GND I/O/Q
I
I/O/Q I I/O/Q
11 19
I
I/O/Q
I/O/Q
I
12 14 16 18
I I/O/Q
14 15 I/O/Q
I
2
Copyright 2000 Lattice Semiconductor Corp. GAL, E CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp. Generic Array Logic is a trademark of Lattice Semiconduc-
tor Corp. The specifications herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 N.E. Moore Ct., Hillsboro, Oregon 97124 U.S.A. November 2000
Tel. (503) 268-8000 or 1-800-LATTICE; FAX (503) 268-8556
ALL DEVICES
DISCONTINUED
I/CLK2
I
I
I
I
I
I
I/O/Q
I
I/O/Q
I
PROGRAMMABLE
I/O/Q
I/O/Q
I/O/Q AND-ARRAY
I/O/Q
(150X52)
I/CLK1